A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24-7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of -107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40-51 mA from the 1.8-V supply and occupies an area of 440 lm 9 430 lm.

A 7-GHz CMOS voltage controlled ring oscillator that employs multiloop technique for frequency boosting is presented in this paper. The circuit permits lower tuning gain through the use of coarse/fine frequency control. The lower tuning gain also translates into a lower sensitivity to the voltage at the control lines. Fabricated in a standard 0.13-m CMOS process, the proposed voltage-controlled ring oscillator exhibits a low phase noise of 103.4 dBc/Hz at 1 MHz offset from the center frequency of 7.64 GHz, while consuming a current of 40 mA excluding the buffer.

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Because of difficulty in deep ion implantation, the recessed gate structure has been favored in SiC SIT. In order to improve the frequency, it is a good method to decrease the gate length by eliminating the side wall ion implantation affection. We developed normally-on RF 4H-SiC SIT with high small signal gain. The effect of forming the side wall protection between the source mesa and the gate area was simulated