AES has been one of the most popular encryption and decryption algorithms for data security applications. At the same time, data randomization (or "homogeneous") technology was applied to reduce the bit error rate (BER) of MLC and TLC flash memory. Here, AES algorithm was found efficient to replace the orthogonal polynomials which normally carry out homogeneous function by scrambling data. This paper put forward a novel hardware architecture providing both homogeneous and data encryption/decryption functions concurrently by an embedded AES hardware engine while getting rid of randomization engine with Linear Feedback Shift Register (LFSR). It made a flash controller simple and reduced the die size because the independent homogeneous hard engine is no longer necessary for a flash memory system, in which AES security algorithm embedded. Finally a SSD controller designed in this architecture was silicon proven.

Solid-state drives (SSDs) for mobile and embedded systems may not provide very high performance by today's standards; however, they are small, low cost and consume little power. SSD controllers are thus designed as DRAM-less chips. SRAM cells created by the IC foundry as a standard module are embedded in the SSD controller as data buffer and can be single-port or two-port. In an SSD controller, more than two IPs simultaneously access the same SRAM, such as the CPU, data interface, and multiflash memory channel. It is thus complicated to exchange data between multiple ports. A new architecture of the multi-port data buffer (M-Buffer) is proposed in this study to solve this problem. M-Buffer is composed of wide SRAM, a smart arbitrator and several interface port logics. The M-Buffer can be designed as a reusable architecture and is small, low cost and consumes little power.

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This paper presents a ring oscillator structure which combines meta-stable states with Fibonacci ring oscillators (FIRO) and Galois ring oscillators (GAROs). Based on the new structure, a true random number generator (TRNG) of 64 bit was created. This new TRNG was verified by FPGA platform with Altera Cyclone IV series chips, and its output has attainted NIST SP800-22 certification. The testing demonstrates that the proposed meta-stable random number generators improve randomness over traditional methodologies.