Semiconductive transition metal dichalcogenides (TMDs) have been considered as next generation semiconductors, but to date most device investigations are still based on microscale exfoliation with a low yield. Wafer scale growth of TMDs has been reported but effective doping approaches remain challenging due to their atomic thick nature. In this work, we report the synthesis of wafer-scale continuous few-layer PtSe 2 films with effective doping in a controllable manner. Chemical component analyses confirm that both n-and pdoping can be effectively modulated through the controlled selenization process. We systematically study the electrical properties of PtSe 2 films by fabricating top-gated field effect transistors (FETs). The device current on/off ratio is optimized in two-layer PtSe 2 FETs, and four-terminal configuration displays a reasonably high effective field effect mobility (14 and 15 cm 2 V -1 s -1 for p-and n-type FETs, respectively) with a nearly symmetric p-and n-type performance. Temperature dependent measurement reveals that the variable range hopping is dominant at low temperature. To further establish the feasible application based on controllable doping of PtSe 2 , a logic inverter and vertically stacked p-n junction arrays are demonstrated. These results validate that PtSe 2 is a promising candidate among the family of TMDs for future functional electronic applications.

2D layered materials (2DLMs) have gained tremendous interest for their potential applications in next-generation electronic, optoelectronic, [1][2][3] and energy devices. Although graphene possesses the highest reported mobility, its gapless nature motivates the pursuit of semiconductive transition metal dichalcogenides (TMDs) such as MoS 2 , [4][5][6] which has been intensively investigated based on mechanically exfoliated sheets. Yet for practical Atomic thin transition-metal dichalcogenides (TMDs) are considered as an emerging platform to build next-generation semiconductor devices. However, to date most devices are still based on exfoliated TMD sheets on a micrometer scale. Here, a novel chemical vapor deposition synthesis strategy by introducing multilayer (ML) MoS 2 islands to improve device performance is proposed. A four-probe method is applied to confirm that the contact resistance decreases by one order of magnitude, which can be attributed to a conformal contact by the extra amount of exposed edges from the ML-MoS 2 islands. Based on such continuous MoS 2 films synthesized on a 2 in. insulating substrate, a top-gated field effect transistor (FET) array is fabricated to explore key metrics such as threshold voltage (V T ) and field effect mobility (μ FE ) for hundreds of MoS 2 FETs. The statistical results exhibit a surprisingly low variability of these parameters. An average effective μ FE of 70 cm 2 V −1 s −1 and subthreshold swing of about 150 mV dec −1 are extracted from these MoS 2 FETs, which are comparable to the best top-gated MoS 2 FETs achieved by mechanical exfoliation. The result is a key step toward scaling 2D-TMDs into functional systems and paves the way for the future development of 2D-TMDs integrated circuits. Field Effect TransistorsThe ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/smll.201803465. application, wafer-scale synthesis of highquality, continuous MoS 2 film is highly desired. Recently, the chemical vapor deposition (CVD) technique has been applied to produce single-layer (1L) MoS 2 films with moderate electrical performance [7][8][9][10] and so far the largest number of logic gates is 115. [11][12][13] Mechanically exfoliated multilayer (ML) MoS 2 have shown improved mobility and drive currents because of thicker channel with higher density of states. [14,15] A smaller bandgap associated with ML-MoS 2 [16,17] is also more appropriate for device performance engineering. [18][19][20] However, it is rather difficult to grow a uniform and continuous multilayer MoS 2 film since precise control of layer number of stacked MoS 2 remains unsolved, [21,22] and vertical growth is limited by the interlayer diffusion rate of S atoms (much slower than in-plane diffusion) and high surface energy. [23] Besides, it is rather difficult to maintain a planar growth in a controllable manner, instead most results simultaneously produce a mixture of monolayer, multilayer, and empty islands. [24,25] Despite the demand of high-quality wa...

process are highly required and under investigation. [7,8] Recently, integrated circuits based on chemical vapor deposition (CVD)-grown wafer-scale MoS 2 , a representative of TMDs, have already been realized, [9,10] which is an important step toward the practical application of lowpower and high-performance 2D electronic devices. However, the fabrication of largescale MoS 2-based circuits still remains a challenge. One of the major limits is the lack of the homogeneous high-k dielectric deposition on the TMDs without dangling bonds. [11-13] Various technical efforts have been proposed to deposit high quality Al 2 O 3 or HfO 2 dielectrics, such as seeding layer, [14] remote plasma treatment, [15] and ultraviolet-ozone exposure. [16] However, due to the existence of interfacial charge traps or dipoles during atomic layer deposition (ALD) process, a significant n-doping effect could be introduced to the TMDs channel after the top dielectric deposition. [14,17] Under this circumstance, it is difficult to realize enhancement-mode (E-mode) field-effect transistors (FETs) with a positive threshold voltage (V T), which is essential for multistage cascaded circuits. [18] Therefore, for all previously reported electrical circuits based on CVD-synthesized MoS 2 , [9,10] the gate-first technique (gate electrodes are beneath dielectric layer and transferred MoS 2 layer) is utilized to avoid the n-doping via the top dielectric deposition on MoS 2 film. Nevertheless, the gate-first technique requires an extra film transfer process in the solution, which is more challenging and rather difficult for scaling up. Nowadays, utilization of new dielectric materials for emerging semiconductors has attracted much research attention. [19-30] For example, poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) as one of the most promising ferroelectric materials, has been used in ferroelectric memories and photodetectors based on 2DLMs. [29,30] It can provide an ultrahigh electrostatic field (nearly 10 9 V m −1) in the remnant polarization. But the ferroelectric material usually requires a high gate voltage (10-20 V) to effectively drive, which greatly limits its application in low-voltage electronics. On the other hand, electrolyte material could be an alternative candidate for nanoelectronics, which can commonly serve as a dielectric layer in the FET structure. Under a positive gate voltage, for example, cations in the electrolyte accumulate at the electrolyte/semiconductor interface, and correspondingly anions gather near the Electrolyte gating, based on the electric double-layer effect, has been widely used for 2D layered materials (2DLMs), since it is capable of inducing an ultrahigh charge-carrier density while requiring only a low gate voltage. However, the wafer-scale fabrication of high-performance field effect transistors (FETs) based on electrolyte gating remains challenging, due to the lack of an appropriate electrolyte film coating technique. Wafer-scale MoS 2 FETs gated by high-quality thin electrolyte film are demonstrat...

Two-dimensional layered materials (2DLMs) have attracted great research interest due to their exotic physical properties and potential applications in nanoelectronics and optoelectronics. Device fabrication with 2DLMs is challenging because their ultrathin characteristic makes them extremely sensitive to the external environment, especially to chemical contamination introduced by optical lithography. The shadow mask technique is a clean alternative in lithography-free electrode patterning for emerging nanomaterials. However, shadow mask assisted fabrication over large areas and multilevel alignment of patterns remain challenging for practical applications. In this paper, we report an over wafer scale shadow mask fabrication technique for 2DLMs. Based on successful fabrication of customized silicon shadow masks with micrometer feature sizes, their advantages for fabricating higher mobility and lower interface trapped exfoliated MoS 2 transistors are demonstrated. Meanwhile, applications in large-scale metal deposition and sample etching are also explored. The max alignment error of multilayer patterns fall in 0.5-3.0 µm in x-and 2.0-9.0 µm in y -directions. Then this technique is employed to realize a fabrication of MoS 2 top-gated field effect transistor arrays with two universal strategies: 'etching-last' and 'channel-first' on 1 × 1 cm 2 Al 2 O 3 substrate. Furthermore, logic inverter circuits with a high gain of 10 are successfully fabricated. The results provide an alternative as a universal, low-cost, time-saving method for fabricating large-scale 2DLM electronics and flexible electronics.