This paper describes a CMOS-based time-of-flight depth sensor and presents some experimental data while addressing various issues arising from its use. Our system is a single-chip solution based on a special CMOS pixel structure that can extract phase information from the received light pulses. The sensor chip integrates a 64x64 pixel array with a high-speed clock generator and ADC. A unique advantage of the chip is that it can be manufactured with an ordinary CMOS process. Compared with other types of depth sensors reported in the literature, our solution offers significant advantages, including superior accuracy, high frame rate, cost effectiveness and a drastic reduction in processing required to construct the depth maps. We explain the factors that determine the resolution of our system, discuss various problems that a time-of-flight depth sensor might face, and propose practical solutions.

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We present a novel method to perform timing analysis of hierarchical circuits. It is based on the representation of circuit modules by conditional delay matrices (CDMs) which combine module delays with event propagation conditions. The CDM model is independent of module complexity and allows automatic identijication of false paths. We exploit hierarchy information to p e~o r m eflcient delay computation. The effectiveness of the method is demonstrated on a high-level model of the ISCAS-85 circuit ~6 2 8 8 , which is difJicult to analyze using traditional approaches. The method has been implemented in a symbolic timing analysis program called CAI: The application of CAT to carry-skip adders shows that hierarchical timing analysis is faster by an order of magnitude than gate-level analysis.

We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Bused on the conditional delay matrix (CDM) formalism we introduced earliel; the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. The signal propagation conditions are restricted to a set of predefined control inputs, which results in SigniJicant reductions in the size of the conditions as well as computation time. We have implemented ACD and experimented with reverse-engineered high-level versions of the ISCAS-85 benchmarks. Our results demonstrate up to three orders of magnitude speedup in computation time over exact methods, with little or no loss in accuracy.

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