The increasing density of NAND flash memories makes data more prone to errors due to severe process variations and disturbance. The urgency to improve NAND flash reliability encourages searching for optimal channel coding methods. This paper reports our efforts towards a read channel for flash memories using polar coding. Our contributions include the solutions to several challenges raised when applying polar codes to NAND flash memories in practice. We propose efficient schemes for shortening both non-systematic and systematic polar codes, making polar codewords be easily adapted to flash page of any size. We demonstrate that the decoding performance of the shortened polar codes and LDPC codes are comparable using the data obtained by our NAND flash characterization platform. We show the feasibility of a practical adaptive decoding framework where it is not necessary to construct new polar codes for different channel parameters. Experimental results show that the decoding performance approaches the optimized performance where different codes are constructed for different channel conditions. To the best of our knowledge, this work is the first study of polar codes for error correction in flash memories.

The error-pattern correction code is a code specialized to correct dominant error patterns observed at the channel detector output in heavy intersymbol interference channels. In this paper, we consider a turbo-equalizer system that utilizes the error-pattern correcting code (EPCC) as a building component. A soft-input soft-output (SISO) decoder for the EPCC is described, and the performance of the proposed turbo equalizer is compared with those of the conventional turbo equalizer and a low density parity check (LDPC) code system.

Abstract-The error pattern correcting code (EPCC) can be constructed to provide a syndrome decoding table targeting the dominant error events of an inter-symbol interference channel at the output of the Viterbi detector. For the size of the syndrome table to be manageable and the list of possible error events to be reasonable in size, the codeword length of EPCC needs to be short enough. However, the rate of such a short length code will be too low for hard drive applications. To accommodate the required large redundancy, it is possible to record only a highly compressed function of the parity bits of EPCC's tensor product with a symbol correcting code. In this paper, we show that the proposed tensor error-pattern correcting code (T-EPCC) is linear time encodable and also devise a low-complexity soft iterative decoding algorithm for EPCC's tensor product with q-ary LDPC (T-EPCC-qLDPC). Simulation results show that T-EPCC-qLDPC achieves almost similar performance to single-level qLDPC with a 1/2 KB sector at 50% reduction in decoding complexity. Moreover, 1 KB T-EPCC-qLDPC surpasses the performance of 1/2 KB single-level qLDPC at the same decoder complexity.Index Terms-Tensor product codes, inter-symbol interference, turbo equalization, error-pattern correction, q-ary LDPC, multi-level log likelihood ratio, tensor symbol signatures, signature-correcting code, detection postprocessing.

The error-pattern correcting code (EPCC) is incorporated in the design of a turbo equalizer (TE) with aim to correct dominant error events of the inter-symbol interference (ISI) channel at the output of its matching Viterbi detector. By targeting the low Hamming-weight interleaved errors of the outer convolutional code, which are responsible for low Euclidean-weight errors in the Viterbi trellis, the turbo equalizer with an error-pattern correcting code (TE-EPCC) exhibits a much lower bit-error rate (BER) floor compared to the conventional non-precoded TE, especially for high rate applications. A maximum-likelihood upper bound is developed on the BER floor of the TE-EPCC for a generalized two-tap ISI channel, in order to study TE-EPCC's signal-to-noise ratio (SNR) gain for various channel conditions and design parameters. In addition, the SNR gain of the TE-EPCC relative to an existing precoded TE is compared to demonstrate the present TE's superiority for short interleaver lengths and high coding rates. Index TermsInter-symbol interference, turbo equalization, dominant error events, error pattern correcting code, maximum-likelihood bit error rate bound, error weight enumerator, list decoding, dicode channel.