This paper introduces an optimal hybrid power filter design method to compensate simultaneously current harmonics and reactive power of a nonlinear load. The hybrid power filter consists of a passive RL low-pass filter placed in series with the load and an active filter which has RL elements connected in series with insulated gate bipolar transistors (IGBT) based voltage source converter. The filter is supposed to inject a current into the connection node of the load and grid in order to eliminate current harmonics and its imaginary current. The voltage source converter is placed in a hysteresis feedback control loop to generate the reference current. The band width and output amplitude of the hysteresis controller are optimized with inductance of RL filters. In solving the optimization problem, three objective functions are considered which include minimizing current total harmonic distortion (THD), maximizing power factor and minimizing the IGBT bridge current. The two optimization methods applied are non-dominated sorting genetic algorithm-II (NSGA-II) and strength Pareto evolutionary algorithm2 (SPEA2) methods. The results of the two optimization methods are compared and it is shown that the SPEA2 method gives the best performance in terms of minimizing current THD, maximizing the power factor and reducing IGBT bridge current.

Innovative processor architectures aim to play a critical role in future sustainment of performance improvements under severe limitations imposed by the end of Moore’s Law. The Reconfigurable Optical Computer (ROC) is one such innovative, Post-Moore’s Law processor. ROC is designed to solve partial differential equations in one shot as opposed to existing solutions, which are based on costly iterative computations. This is achieved by leveraging physical properties of a mesh of optical components that behave analogously to lumped electrical components. However, virtualization is required to combat shortfalls of the accelerator hardware. Namely, 1) the infeasibility of building large photonic arrays to accommodate arbitrarily large problems, and 2) underutilization brought about by mismatches in problem and accelerator mesh sizes due to future advances in manufacturing technology. In this work, we introduce an architecture and methodology for light-weight virtualization of ROC which exploits advantages borne from optical computing technology. Specifically, we apply temporal and spatial virtualization to ROC and then extend the accelerator scheduling tradespace with the introduction of spectral virtualization. Additionally, we investigate multiple resource scheduling strategies for a system-on-chip (SoC)-based PDE acceleration architecture and show that virtual configuration management offers a speedup of approximately 2 ×. Finally, we show that overhead from virtualization is minimal, and our experimental results show two orders of magnitude increased speed as compared to microprocessor execution while keeping errors due to virtualization under 10%.

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