Coxiella burnetii, the agent of Q fever, enters human monocytes through ␣ v  3 integrin and survives inside host cells. In addition, C. burnetii stimulates the synthesis of inflammatory cytokines including tumor necrosis factor (TNF) by monocytes. We studied the role of the interaction of C. burnetii with THP-1 monocytes in TNF production. TNF transcripts and TNF release reached maximum values within 4 h. Almost all monocytes bound C. burnetii after 4 h, while the percentage of phagocytosing monocytes did not exceed 20%. Cytochalasin D, which prevented the uptake of C. burnetii without interfering with its binding, did not affect the expression of TNF mRNA. Thus, bacterial adherence, but not phagocytosis, is necessary for TNF production by monocytes. The monocyte ␣ v  3 integrin was involved in TNF synthesis since peptides containing RGD sequences and blocking antibodies against ␣ v  3 integrin inhibited TNF transcripts induced by C. burnetii. Nevertheless, the cross-linking of ␣ v  3 integrin by specific antibodies was not sufficient to induce TNF synthesis. The signal delivered by C. burnetii was triggered by bacterial lipopolysaccharide (LPS). Polymyxin B inhibited the TNF production stimulated by C. burnetii, and soluble LPS isolated from C. burnetii largely mimicked viable bacteria. On the other hand, avirulent variants of C. burnetii induced TNF production through an increased binding to monocytes rather than through the potency of their LPS. We suggest that the adherence of C. burnetii to monocytes via ␣ v  3 integrin enables surface LPS to stimulate TNF production in THP-1 monocytes.
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Prohibitive simulation time of single multiprocessor configuration makes large design space exploration impossible without massive use of computing resources and still implementation issues are not tackled. This paper proposes a new performance evaluation methodology for multiprocessors on chip which conduct a multiobjective design space exploration through emulation. The proposed approach is validated on a 4 way multiprocessor on chip design space exploration where a 6 order of magnitude improvement have been achieved over cycle accurate simulation.
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