No abstract

No abstract

ArF lithography is essential to develop a sub-100 nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER/LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER/LWR to device performance so that the reasonable control range of LER/LWR can be defined. To implement the experiment, 80 nm node of single NMOS transistors were fabricated, which had various range of gate length, width, and LER/LWR. The amount of LER/LWR could be successfully controlled by applying different resist materials, defocus, and over etch time. Experimental results show that leakage current is significantly increased when LWR is greater than 10 nm. In addition, it is observed that both threshold voltage and on-off current variation get increased exponentially as gate width decreases.

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the leading candidates for low-k 1 lithography, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications [4,5] , it has been shown that the Inverse Synthesizer (IS™) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask.The production readiness of ILT has been demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to further reduce ILT mask complexity without compromising too much of process window. These areas include flexible controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these approaches on e-beam mask writing time and lithography performance is presented in the paper.

No abstract