Achieving low contact resistance (RC) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS2 devices are systematically analyzed as a function of top and bottom gate‐voltages (VTG and VBG). The semimetal contacts not only significantly reduce RC but also induce a strong dependence of RC on VTG, in sharp contrast to Ti contacts that only modulate RC by varying VBG. The anomalous behavior is attributed to the strongly modulated pseudo‐junction resistance (Rjun) by VTG, resulting from weak Fermi level pinning (FLP) of Sb contacts. In contrast, the resistances under both metallic contacts remain unchanged by VTG as metal screens the electric field from the applied VTG. Technology computer aided design simulations further confirm the contribution of VTG to Rjun, which improves overall RC of Sb‐contacted MoS2 devices. Consequently, the Sb contact has a distinctive merit in dual‐gated (DG) device structure, as it greatly reduces RC and enables effective gate control by both VBG and VTG. The results offer new insight into the development of DG 2D FETs with enhanced contact properties realized by using semimetals.

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (IOFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by −16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.

In this work, performance comparison of various architectures of field-effect transistors (FETs) introduced with transition metal dichalcogenide (TMDC) MoS2 channels, which is attracting attention as one of the technologies that will enable beyond-silicon technology, was performed. By performing circuit-level benchmark for dynamic logic circuit operation in sub-2 nm dimension, it is observed that the optimal FET structure differs according to MoS2 layer numbers. When two or more multilayer MoS2 is applied to a double-gate and multistacked channel FET structure, the capacitance increases due to the increase in structure complexity, but the improvement of the current is greater, and the circuit operation speed increases. It is similar to the scaling-down trend of silicon-based FETs. However, in the case of monolayer MoS2, a simple single-gate planar FET structure shows optimal circuit characteristics, which is analyzed to be due to the excellent short-channel effect immunity of the monolayer MoS2 channel and small parasitic capacitance. Layout effects such as fan-out numbers and wiring load in integrated logic circuits were also investigated in various MoS2-FET structures. In addition, reliability analysis was performed through electrothermal simulation of thermal issues related to the multigate transistor structure.

A poly (3,6‐bis(thiophen‐2‐yl)−2,5‐bis(2‐decyltetradecyl)−2,5‐dihydropyrrolo[3,4‐c]pyrrole‐1,4‐dione‐co‐(2,3‐bis(phenyl)acrylonitrile)) (PDPADPP) copolymer, composed of diketopyrrolopyrrole (DPP) and a cyano (nitrile) group with a vinylene spacer linking two benzene rings, is synthesized via a palladium‐catalyzed Suzuki coupling reaction. The electrical performance of PDPADPP in organic field‐effect transistors (OFETs) and circuits is investigated. The OFETs based on PDPADPP exhibit typical ambipolar transport characteristics, with the as‐cast OFETs demonstrating low field‐effect hole and electron mobility values of 0.016 and 0.004 cm2 V−1 s−1, respectively. However, after thermal annealing at 240 °C, the OFETs exhibit improved transport characteristics with highly balanced ambipolar transport, showing average hole and electron mobility values of 0.065 and 0.116 cm2 V−1 s−1, respectively. To verify the application of the PDPADPP OFETs in high‐voltage logic circuits, compact modeling using the industry‐standard small‐signal Berkeley short‐channel IGFET model (BSIM) is performed, and the logic application characteristics are evaluated. The circuit simulation results demonstrate excellent logic application performance of the PDPADPP‐based ambipolar transistor and illustrate that the device annealed at 240 °C exhibits ideal circuit characteristics.