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Abstract-The SARUS scanner (Synthetic Aperture Real-time Ultrasound System) for research purposes is described. It can acquire individual channel data for multi-element transducers for a couple of heart beats, and is capable of transmitting any kind of excitation. It houses generous and flexible processing resources that can be reprogrammed and tailored to many kinds of algorithms. The 64 boards in the system house 16 transmit and 16 receive channels each, where data can be stored in 2 GB of RAM and processed using four Virtex 4FX100 and one FX60 FPGAs. The VHDL code can acquire data for 16 channels and perform real-time processing for four channels per board. The receive processing chain consists of three FPGAs. The beamformer FPGA houses 24 focusing units (6 x 4-way) each working in parallel at 220 MHz for parallel four-channel beamforming. The fully parametric focusing unit calculates delays and apodization values in real time in 3D space and can produce 630 million complex samples per second. The processing can, thus, beamform 192 image lines consisting of 1024 complex samples for each emission at a rate of 3200 frames a second yielding full nonrecursive synthetic aperture B-mode imaging at more than 30 high resolution images a second.

Abstract-Synthetic Aperture (SA) ultrasound imaging has many advantages in terms of flexibility and accuracy. One of the major drawbacks is, however, that no system exists, which can implement SA imaging in real time due to the very high number of calculations amounting to roughly 1 billion complex focused samples per second per receive channel. Real time imaging is a key aspect in ultrasound, and to truly demonstrate the many advantages of SA imaging, a system usable in the clinic should be made. The paper describes a system capable of real time SA Bmode and vector flow imaging. The Synthetic Aperture Real-time Ultrasound System (SARUS) has been developed through the last 2 years and can perform real time SA imaging and storage of RF channel data for multiple seconds. SARUS consists of a 1024 channel analog front-end and 64 identical digital boards. Each has 16 transmit channels and 16 receive channels both with a sampling frequency of 70 MHz/12 bits for arbitrary waveform emission and reception. The board holds five Virtex 4FX100 FPGAs, where one houses a PowerPC CPU used for control. The remaining four are used for generation of transmit signals, receive storage and matched filter processing, and focusing and summing of data. Each FPGA can perform 80 billion multiplications/s and the full system can perform 25,600 billion multiplications/s. The FPGAs are connected through multiple 3.2 Gbit Rocket IO links, which makes it possible to send more than 1.6 GBytes/s of data between the FPGAs and between boards. The system can concurrently sample in 1024 channels, thus, generating 140 GBytes/s of data, which also can be processed in real time or stored. The system is controlled over a 1 Gbit/s Ethernet link to each digital board that runs Linux. The control and processing are divided into functional units that are accessed through an IP numbering scheme in a hierarchical order. A single controlling mechanism can, thus, be used to access the whole system from any PC. It is also possible for the controlling PowerPCs to access all other boards, which enables advanced adaptive imaging. The software is written in C++ and runs under Matlab for high level access to the system in a command structure similar to the Field II simulation program. This makes it possible for the user to specify imaging in very few lines of code and the set-up is fast due to the employment of the 64 PowerPCs in parallel. Focusing is done using a parametric beam former. Code synthesized for a Xilinx V4FX100 speed grade 11 FPGA can operate at a maximum clock frequency of 167.8 MHz producing 1 billion I and Q samples/second sufficient for real time SA imaging. The system is currently in production, and all boards have been laid out. VHDL and C++ code for the control has been written and the code for real time beamformation has been made and has obtained a sufficient performance for real-time imaging.

In this paper we want to analyze how the high-level languages Java and VRML can be used for 3D medical imaging and simulation on a PC. We want to compare two different approaches to use Java combined with VRML. One approach is to use Java locally inside VRML (JSAI), the other is to control a VRML environment externally from Java (EAI). We also examine the usefulness of VRML animation used for surgery simulation.First we describe a VRML centered application using Java for behavior processing through the JSAI script interface. This is done using the best publicly available browsers. This approach causes problems due to difficulties in handling the very complex models needed and in the limited Java support.A second implementation is centered around a Java application, where the VRML browser is handled as a Java component. The VRML browser is controlled from Java through the EAI external application interface. VRML animation is used in both prototypes. We use our in-house developed VRML library Hybris for the second implementation, where we have full control over the VRML engine and rendering engine which allows better handling of larger models.

This paper discusses the trade-off between calculations and memory accesses in a 3D graphics tile renderer for visualization of data from medical scanners. The performance requirement of this application is a frame rate of 25 frames per second when rendering 3D models with 2 million triangles, i.e. 50 million triangles per second, sustained (not peak). At present, a software implementation is capable of 3-4 frames per second for a 1 million triangle model. By using direct evaluation of certain interpolation parameters instead of forward differencing, writing back parameters to SDRAM is avoided. In software, forward differencing is usually better, but in this hardware implementation, the trade-off has made it possible to develop a very regular memory architecture with a buffering system, which can reach 95% bandwidth utilization using offthe-shelf SDRAM. This is achieved by changing the algorithm to use a memory access strategy with write-only and read-only phases, and a buffering system, which uses round-robin bank write-access combined with burst read-access.