This paper presents an ultra-low-power (ULP) fully-integrated Bluetooth Low-Energy(BLE)/IEEE802.15.4/proprietary RF SoC for Internet-of-Things applications. Ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life. A ULP RF transceiver [1-3] is one of the most critical components that enables these emerging applications, as it can consume up to 90% of total battery energy. Furthermore, a low-cost radio design with an area-efficient fully integrated RF SoC is an important catalyst for developing such applications. By employing a low-voltage digital-intensive architecture, the presented SoC is fully compliant with BLE and IEEE802.15.4 PHY/Data-link requirements and achieves state-of-the-art power consumption of 3.7mW for RX and 4.4mW for TX. Figure 13.2.1 shows the architecture of the RF SoC. An all-digital TX consists of a sub-mW snapshot-TDC all-digital PLL (ADPLL) [4] and an energy-efficient Class-D PA. A sliding-IF RX is adopted because it does not require a powerhungry LO generation. The PA with partial on-chip impedance matching and the LNA are both single-ended, which reduce external components and simplify the antenna interface design. A multistandard DBB [5] includes all PHY processing and data link for BLE and IEEE802.15.4. In this work the DBB further includes optimized HW/SW register interfaces and HW accelerators for protocol support, and implements an AHB/APB interface to facilitate integration with an ARM Cortex TM -M0 MCU and 128kB SRAM.One of the most challenging parts of the BLE RX mode is to receive the packets with an extremely short 8b preamble, which requires fast automatic gain control (AGC) and carrier-frequency offset (CFO) compensation method. A two-step AGC algorithm performs only coarse gain tuning in the RF parts (i.e., LNA and mixers) during the preamble with 12dB/step, allowing the RX output amplitude to quickly settle within the ADC dynamic range in just a few symbol periods. The fine amplitude tuning is performed in the LPF/PGA during the access code period with 3dB/step. Furthermore, BLE also specifies that the RX should accommodate a "dirty TX" with a large CFO up to ±100kHz (±41ppm). The CFO could be post-compensated in the DBB with a phase rotator, but then the LPF BW needs to be at least 100kHz wider, which compromises the adjacent channel rejection. In this work, a mixed-mode CFO compensation through an ADPLL allows direct compensation in the analog domain without increasing LPF BW. The CFO is first estimated by the DBB based solely on a part of the packet's preamble. The CFO estimation unit employs a 17-tap FIR filter with low latency. The CFO is detected by converting the IQ data to phase difference, and averaging it across preamble symbols. The CFO is then compensated by directly adjusting the fractional-N ADPLL with a frequency resolution of 1kHz. However, PLLs typically have a slow settling in the order of 20μs, which is not fast enough to compensate the CFO within the preamble. Therefore, the 2-point injection technique emp...

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We show that continuously monitoring on-chip delays at the LUT-to-LUT link level during operation allows a field-programmable gate array to detect and self-adapt to aging and environmental timing effects. Using a lightweight (<4% added area) mechanism for monitoring transition timing, a Difference Detector with First-Fail Latch, we can estimate the timing margin on circuits and identify the individual links that have degraded and whose delay is determining the worst-case circuit delay. Combined with Choose-Your-own-Adventure precomputed, fine-grained repair alternatives, we introduce a strategy for rapid, in-system incremental repair of links with degraded timing. We show that these techniques allow us to respond to a single aging event in less than 190ms for the toronto20 benchmarks. The result is a step toward systems where adaptive reconfiguration on the time-scale of seconds is viable and beneficial.

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Failing network links are usually disabled, and packets are routed around them until the links are repaired. While it is often possible to utilize some of a failing link's capacity, losing what remains of a link's capacity is typically deemed preferable to the erratic effect that unreliable links can have on application-level behavior. We describe a new network function that relies on in-network computing to limit the erratic effect of failing network links, to enable the continued use of those links until they can be repaired. We explore the design space using ns-3, and evaluate our implementation on a physical test-bed that includes programmable switches and reconfigurable hardware. Our current hardware prototype can almost saturate a 10GbE link while using around 10% of our FPGA's resources.