This paper proposes a new ladder-switch based cascaded multilevel inverter that requires a lower number of insulated gate bipolar transistors (IGBTs) and direct current (DC) voltage sources to generate a specified range of voltage levels. Regarding this topology, it consists of λ stages, where each stage comprises k legs, besides each leg composed of n cells. So, the proposed topology can be optimized to obtain the lower requirement for IGBTs and DC voltage sources. It is required to mention that this topology generates both negative and positive voltage levels inherently. Two different algorithms are presented to synthesize all odd and even voltage levels. After, regarding each of the algorithms, the proposed topology is optimized from different aspects of the lowest number of IGBTs or the lowest number of DC voltage sources, and results are depicted. A comparison assessment is performed to find the advantages and possible disadvantages of the proposed topology. In the end, a 23-level prototype of the proposed topology is used to validate the correct performance of the proposed topology using the experimental results.

In this paper, a modified topology for developing H-bridge inverter is proposed which the number of components is lower than other inverters as well as the proposed inverter generates a high number of level with low total harmonics distortions. In the first, the new developed h-bridge inverter is proposed and then a cascaded connection of this inverter to increase the number of levels is presented. Three different methods are proposed to determine the DC power sources magnitudes and among them, the best algorithm is chosen for comparison the proposed cascaded inverter with other cascaded inverters. Finally, the proposed cascaded inverter consist of two proposed basic inverters to generate thirty-three voltage levels is simulated to evaluate the performance of the proposal.Index Terms-developed H-bridge inverter; cascaded inverter; reduced components.

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