This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC decoder based on the de Bruijn network. The main characteristics of this networkincluding its logarithmic diameter, scalable aggregate bandwidth, and optimized routing technique-allow it to efficiently support the communication intensive nature of the application. We present a detailed hardware implementation of the routers and the network interfaces as well as the packet format and the routing algorithm. The latter is a parallelized version of the shortest path with deflection routing algorithm. In order to evaluate the performance of the proposed network, a generic RTL VHDL description has been developed and synthesized with CMOS STMicroelectronics 0.18 µm technology. The flexibility and the scalability of this onchip communication network enable it to be used for any kind of LDPC code.

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This paper proposes a novel on-chip interconnection network adapted to a flexible multiprocessor LDPC/turbo decoder and based on the de Bruijn network. The main characteristics of this network -including its logarithmic diameter, scalable aggregate bandwidth, and optimized routing technique-allow it to efficiently support the communicationintensive nature of the two decoding techniques. We present a detailed hardware implementation of the routers and the network interfaces as well as the packet format and the routing algorithm. In order to evaluate the performance of the proposed network, a generic RTL VHDL description has been developed and synthesized with ST CMOS 0.18 µm technology. The flexibility and the scalability of this on-chip communication network enable it to be used in the emerging multi-code applications and standards. In addition, the results obtained for a 16-processor network demonstrate a major aggregate bandwidth of 296 Gbps with a relative small area of 3.56 mm².

International audienc

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