Recent electronic applications require an efficient computing system that can perform data processing with limited energy consumption. Inspired by the massive parallelism of the human brain, a neuromorphic system (hardware neural network) may provide an efficient computing unit to perform such tasks as classification and recognition. However, the implementation of synaptic devices (i.e., the essential building blocks for emulating the functions of biological synapses) remains challenging due to their uncontrollable weight update protocol and corresponding uncertain effects on the operation of the system, which can lead to a bottleneck in the continuous design and optimization. Here, we demonstrate a synaptic transistor based on highly purified, preseparated 99% semiconducting carbon nanotubes, which can provide adjustable weight update linearity and variation margin. The pattern recognition efficacy is validated using a device-to-system level simulation framework. The enlarged margin rather than the linear weight update can enhance the fault tolerance of the recognition system, which improves the recognition accuracy.

Inspired by the human brain, a neuromorphic system combining complementary metal-oxide semiconductor (CMOS) and adjustable synaptic devices may offer new computing paradigms by enabling massive neural-network parallelism. In particular, synaptic devices, which are capable of emulating the functions of biological synapses, are used as the essential building blocks for an information storage and processing system. However, previous synaptic devices based on two-terminal resistive devices remain challenging because of their variability and specific physical mechanisms of resistance change, which lead to a bottleneck in the implementation of a high-density synaptic device network. Here we report that a three-terminal synaptic transistor based on carbon nanotubes can provide reliable synaptic functions that encode relative timing and regulate weight change. In addition, using system-level simulations, the developed synaptic transistor network associated with CMOS circuits can perform unsupervised learning for pattern recognition using a simplified spike-timing-dependent plasticity scheme.

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Neuromorphic systems (hardware neural networks) derive inspiration from biological neural systems and are expected to be a computing breakthrough beyond conventional von Neumann architecture. Interestingly, in neuromorphic systems, the processing and storing of information can be performed simultaneously by modulating the connection strength of a synaptic device (i.e., synaptic weight). Previously investigated synaptic devices can emulate the functionality of biological synapses successfully by utilizing various nano-electronic phenomena; however, the impact of intrinsic synaptic device variability on the system performance has not yet been studied. Here, we perform a device-tosystem level simulation of different synaptic device variation parameters in a designed neuromorphic system that has the potential for unsupervised learning and pattern recognition. The effects of variations in parameters such as the weight modulation nonlinearity (NL), the minimum-maximum weight (G min and G max ), and the weight update margin (ΔG) on the pattern recognition accuracy are analyzed quantitatively. These simulation results can provide guidelines for the continued design and optimization of a synaptic device for realizing a functional large-scale neuromorphic computing system.The mammalian neocortex offers extremely energy-efficient information processing performance in tasks such as pattern recognition with a power consumption of only 10-20 watts 1 . By mimicking both the functional and structural advantages of this biological neural system, the recent development of power-efficient computing systems, i.e., neuromorphic systems (hardware neural networks) 2 , has been expected to offer a promising breakthrough for applications, ranging from mobile platforms 3 to artificial intelligence operations 4 , where power consumption is a concern.A unique feature of neuromorphic systems is efficient parallel data processing, where the processing of information can be performed by modulating the connection strength of synapses (referred to as the synaptic weight) 5 . This synaptic weight can be modulated by either potentiating or depressing neural spikes (pulses) from pre-and post-synaptic neurons, following appropriate learning rules, such as spike-timing-dependent plasticity (STDP) 6 . Therefore, a key element in the neuromorphic system is the implementation of an ideal synaptic device that can emulate the functionality of biological synapses.To date, various nano-electronic devices have successfully reproduced a specific learning rule of biological synapses through their internal analog conductance states that can be modulated intentionally with an applied pulse's timing or level [7][8][9][10][11][12][13][14][15] . Moreover, the potential of ultralow energy consumption per synaptic operation 16 , as well as the possibility of realizing three-dimensional integration 17 , have shown the promising feasibility of large-scale neuromorphic system implementation in the near future. However, the sustainability of such devices is still in dou...

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