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This paper presents part of the results obtained after conducting an experiment designed with the help of the Design of Experiments (DoE) method. The aim of this experiment is to evaluate the dependencies between the layout design and the production quality of surface mount (SMT) boards. A test board was specially designed to allow us to vary certain factors. The DoE method was used to plan the variation of these factors in order to see their influences on the responses. The responses analyzed until now are: number of tombstones, wetting area, stand-off and existence of solder balls. The test was performed with 108 boards, two stencils, three solder pastes and three thermal profiles. Preliminary results show very few tombstones and good wetting areas for all three solder pastes in case of convection reflow. The heights for all components were measured before and after soldering. The analysis of the values obtained for the same chip component reveals that the stand-off difference (as we defined it) has the smallest value when the pad width is smaller than standard. Thus, the influence of the layout design on the quality of SMT boards can be observed.

The main goals of quality management in all industries are customer satisfaction by delivery of defect-free products, the radical reduction of defect rates and also of quality costs in the production. Controlled technological processes are the most important way to reach these goals. These principles are standard in mechanical engineering and are in use with great success. The properties in electronics production are different from the properties in mechanical engineering. The processes are dificult and many environmental influences act on these processes. These influences are very strong, especially in production of small batches of assemblies (high mix -low volume). Some processes can be uncontrolled and the defect rates go up. What can we do with these processes? We need tools to compare the quality behaviors of different technological processes caused by different electronic products. What is the correct inspection strategy -no inspection or 100% inspection or Statistical Process Control (SPC) ? To answer these question we have developed easy to use quality cost models. The quality costs are the "measurement system" to compare different inspection strategies with each other. The costs are calculated by the use of mathematical models -the quality cost models. We presented the "linear" cost models at ISSE I999 in Dresden. These models contain also the influence of pseudo defects and defect flow at the inspection processes. The reason to use these quality cost models is to get a decision aid in test process organization (100% inspection, SPC or no inspection afer a considered technological process). In the case of SPC it is possible to get an adapted sampling plan.The investigations were made in cooperation with the electronics production of a big intemational enterprise. The basic quality cost models and the extension for SPC will be explained in our presentation. The implementation, the successful use and the economical results of using these models will be presented.

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