Many cryptographic attacks are capable to break RC4. Still RC4 becomes alive in crypto community with several variants. Insufficient key schedule is the most important weakness of RC4 where the first bytes of output reveals information about the key. The loop-holes can be corrected by discarding initial portion of the output stream [1] which is known as RC4-dropN (N is a multiple of 256, such as 768 or 1024). Here we shows RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffling (PKRS) process is introduced between KSA and PRGA. The PKRS process is tuned to form as many S-boxes as required by particular design architectures involving multiple coprocessors, each one undertaking byte-by-byte processing. Following a recent idea [2, 3] the speed of execution of each processor is also enhanced by another fold if the byte-by-byte processing is replaced by a scheme of processing two consecutive bytes together. Adopting some new innovative concepts, three hardware design architectures are proposed in a suitable FPGA embedded system involving 1, 2 and 4 coprocessors functioning in parallel and a study is made on accelerating RC4 by processing bytes in byte-by-byte mode achieving throughputs from 1-byte-in-1-clock to 4-bytes-in-1-clock. The hardware designs are appropriately upgraded to accelerate RC4 further by processing 2 consecutive RC4 bytes together and it has been possible to achieve a maximum throughput of 8-bytes per clock in Xilinx Virtex-5 LX110t FPGA [4] architecture followed by secured communication High Energy Physics (HEP) application that preserves the DC-balancing of the link and permits forward error correction (FEC) along with encryption.

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