In very-large multiple-input multiple-output (MIMO) systems, the base station (BS) is equipped with very large number of antennas as compared to previously considered systems. There are various advantages of increasing the number of antennas, and some schemes require handling large matrices for joint processing (pre-coding) at the BS. The dirty paper coding (DPC) is an optimal pre-coding scheme and has a very high complexity. However, with increasing number of BS antennas, linear pre-coding performance tends to that of the optimal DPC. Although linear pre-coding is less complex than DPC, there is a need to compute pseudo inverses of large matrices. In this paper we present a low complexity approximation of down-link Zero Forcing (ZF) linear pre-coding for very-large multiuser MIMO systems. Approximation using a Neumann series expansion is opted for inversion of matrices over traditional exact computations, by making use of special properties of the matrices, thereby reducing the cost of hardware. With this approximation of linear pre-coding, we can significantly reduce the computational complexity for large enough systems, i.e., where we have enough BS antenna elements. For the investigated case of 8 users, we obtain 90% of the full ZF sum rate, with lower computational complexity, when the number of BS antennas per user is about 20 or more.

This paper describes a hardware efficient linear precoder for Massive MIMO Base Stations (BSs) comprising a very large number of antennas, say, in the order of 100s, serving multiple users simultaneously. To avoid hardware demanding direct matrix inversions required for the Zero-Forcing (ZF) precoder, we use low complexity Neumann series based approximations. Furthermore, we propose a method to speed-up the convergence of the Neumann series by using tri-diagonal precondition matrices, which lowers the complexity even further. As a proof of concept a flexible VLSI architecture is presented with an implementation supporting matrix inversion of sizes up-to 16 × 16. In 65 nm CMOS, a throughput of 0.5M matrix inversions per sec is achieved at clock frequency of 420 MHz with a 104K gate count.

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