This paper introduces a new extension to the DEVS formalism, called Rational Time-Advance DEVS. The basic idea of this new formalism is to permit modeling the behavior of systems that can be modeled by classical DEVS; however, RTA-DEVS models could be formally checked with standard model-checking algorithms and tools. In order to do so, we introduce a procedure to create Timed Automata models that are behaviorally equivalent to the original RTA-DEVS models. This therefore, enables the use of the available TA tools and theories for formal model checking. I. INTRODUCTIONReal-time embedded systems (RTS) are very advanced computer system applications with hardware and software components interacting in a tight fashion. RTS are highly reactive systems where the decisions taken can lead to catastrophic consequences for goods or lives; hence, correctness, and the timing of the executing tasks are critical.An effective approach in studying such systems is to model the application by abstracting unnecessary details, obtaining a model that closely approximates the behavior of the real system. The model would then be studied to reason about the real system. A modeler would select a suitable formalism and tools depending on the nature of the system under study. For instance, continuous systems have a long tradition of being modeled with a algebraic, differential and partial differential equations, which can faithfully model the systems and have well-known methodologies and tools available. For discrete-event systems, formal methods can be used to determine the model's behavior to reason about the real system. Formal verification methods allow the model to be rigorously checked against a specification property, proving if the property is satisfied or not. For instance, Timed Automata (introduced in the 1990's as an extension to finite automata) can be used to model discrete-event systems and their timing aspects [1].TA has an established theory of formal verification and analysis through model-checking [2] [3]. This method tests a model against given specifications or properties using algorithms to formally verify and prove that a model meets a specification (coded as a logic formula), or if not, it can show the sequence of events to cause the defect. The main advantage of model-checking is that it is usually very difficult (or impossible) to test all possible executions of a model to find a defect. Instead, models checked formally are guaranteed to be free of errors (as opposed to simulation and testing based solutions, which gives a certain confidence in a model with no absolute guarantee). However, model-checking algorithms suffer from a state explosion problem, in which total number of states to be checked grows exponentially with the model size. Thus, for large size applications, model-checking is impractical.In these cases, Modeling and Simulation (M&S) techniques and tools can be used for analyzing varied scenarios. In

Real-time systems modeling and verification is a complex task. In many cases, formal methods have been employed to deal with the complexity of these systems, but checking those models is usually unfeasible. Modeling and simulation methods introduce a means of validating these model’s specifications. In particular, Discrete Event System Specification (DEVS) models can be used for this purpose. Here, we introduce a new extension to the DEVS formalism, called the Rational Time-Advance DEVS (RTA-DEVS), which permits modeling the behavior of real-time systems that can be modeled by the classical DEVS; however, RTA-DEVS models can be formally checked with standard model-checking algorithms and tools. In order to do so, we introduce a procedure to create timed automata (TA) models that are behaviorally equivalent to the original RTA-DEVS models. This enables the use of the available TA tools and theories for formal model checking. Further, we introduce a methodology to transform classic DEVS models to RTA-DEVS models, thus enabling formal verification of classic DEVS with an acceptable accuracy.

Rational Time-Advance DEVS (RTA-DEVS) is an extension to DEVS that enables formal verification of simulation models using standard model-checking algorithms and tools. In order to enable formal verification of DEVS models, we introduce a procedure to approximate DEVS with RTA-DEVS. We include conditions for valid approximation and a calculation method for approximation errors that may be introduced. The resulting RTA-DEVS models are behaviorally equivalent to the original DEVS.

8We propose a method to analyze complex physical systems using two-dimensional Cell-DEVS models. These problems 9 are usually modeled with one or more Partial Differential Equations and solved using numerical methods. Our goal is to 10 improve the definition of such problems by mapping them into the Cell-DEVS formalism, which permits easy integration 11 with models defined with other formalisms, and its definition using advanced modeling and simulation tools. To show this, 12 we used two methods for solving PDEs, and deduced the updating rules for their mapping to Cell-DEVS. As our simu-

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