We demonstrate the impact of atomic-layer-deposited TiN gate on the characteristics of W/TiN/SiO2/p-Si metal–oxide–semiconductor (MOS) systems. Damage-free gate oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (Dit) as low as ∼4×1010 eV−1 cm−2 near the Si midgap. ALD–TiN improved the Dit level of MOS systems on both thin SiO2 and high-permittivity (high-k) gate dielectrics. The leakage current of a MOS capacitor gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving gate oxide reliability, paving a way for the direct metal gate process.

We report the effects of the TiN deposition technique on the generation and annihilation of interface traps and oxide trapped charges in W/TiN/SiO 2 ͑2-6 nm͒/Si metal oxide semiconductor ͑MOS͒ system during direct metal gate process. The TiN films were prepared by reactive sputtering using the Ti target or chemical vapor deposition ͑CVD͒ using TiCl 4 and NH 3 . Sputterdeposited TiN not only generated a high level of interface traps ϳ2 ϫ 10 12 eV Ϫ1 cm Ϫ2 from the bandedge to the near midgap of Si, but also introduced oxide trapped charges (Q ot ) of ϳ1 ϫ 10 12 cm Ϫ2 . The damages annealed out for SiO 2 ͑у3 nm͒ to the range of 2 -3 ϫ 10 11 eV Ϫ1 cm Ϫ2 by the post-metal anneal ͑PMA͒ at 800°C in N 2 or at 450°C in forming gas. The interfacial damages for ultrathin SiO 2 ͑ϳ2 nm͒, however, were hardly capable of relieving even after the PMA of 800°C, resulting in an interface trap density (D it ) in the high 10 11 eV Ϫ1 cm Ϫ2 range. The D it level created after CVD-TiN was as low as ϳ3 ϫ 10 11 eV Ϫ1 cm Ϫ2 with negligible Q ot even without PMA, and this level was further reduced to ϳ1 ϫ 10 11 eV Ϫ1 cm Ϫ2 after PMA. We observed a noticeable increase of the capacitance equivalent thickness when prepared with CVD-TiN plausibly due to Cl from the source gas.With scaling complementary metal-oxide-semiconductor ͑CMOS͒ devices to the 100 nm regime, gate depletion and high gate resistance have become a significant problem for polycrystalline-Si ͑poly-Si͒ gate on ultrathin gate oxide. 1-3 The poly-Si gate depletion in conjunction with boron penetration is especially troublesome for p-type poly-Si on thin SiO 2 ͑Ͻ3 nm͒. One approach to overcome these problems is to use a metal gate electrode deposited directly on the gate dielectrics. [2][3][4][5][6][7][8][9][10][11][12][13] A series of advanced researches on direct metal gates were carried out using W, 4 Mo, 5 WN x , 6 TiN x , 2,6-10 and other metals on SiO 2 . 11-13 Buchanan et al. reported W midgap metal gate compatible with ultrathin dielectric ͑ϳ3 nm͒ and demonstrated symmetric flatband voltages for n-and p-type substrate with a barrier height of 3.70 eV. 4 Some interesting results such as generation of interface traps and reliability degradation of MOS devices due to metal penetration and ion damage during the physical vapor deposition ͑PVD͒ process were presented. 4,5,10-12 To anneal the aforementioned defects, the MOS structures gated with direct metals were subjected to a post-metal anneal ͑PMA͒ at high temperatures or in a forming gas anneal ͑FGA͒. 4,5,[10][11][12] Most recently, the feasibility of W/TiN gate stack has been evaluated for conventional 130 nm CMOS technology and beyond. 3,7-10 W/TiN stack is of technological importance because of its midgap work function, low resistivity, and good diffusion barrier properties. 7-9 While PVD-TiN films sputtered at high temperature showed better electrical properties than those prepared at room temperature, 3 PVD-Mo films deposited at room temperature exhibited less metal penetration and damage. 5 Chemical vapor deposition...