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This paper proposes an ultra fine-grained run-time power gating of on-chip router, in which power supply to each router component (e.g., VC queue, crossbar MUX, and output latch)

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Semi-supervised anomaly detection is an approach to identify anomalies by modeling the distribution of normal data. Nowadays, backpropagation neural networks (i.e., BP-NNs) based approaches have been drawing attention because of their high generalization performance for a wide range of real-world data. In a typical application, such BP-NN-based models are iteratively optimized in server machines with a large amount of data gathered from edge devices. However, there are two issues in this framework: (1) BP-NNs' iterative optimization approach often takes too long a time to follow time-series changes of the distribution of normal data (i.e., concept drift), and (2) data transfers between the server machines and the edge devices have a risk to cause data breaches. To address these issues, we propose an ON-device sequential Learning semi-supervised Anomaly Detector called ONLAD and its FPGA-based IP core called ONLAD Core so that various kinds of resource-limited edge devices can use our approach. Experimental results show that ONLAD has favorable anomaly detection capability especially in an environment which simulates concept drift. Evaluations of ONLAD Core confirm that it can perform training and prediction computations faster than BP-NN-based software implementations by x1.95 ∼ x4.51 and x2.29 ∼ x4.73, respectively. We also demonstrate that our on-board implementation which integrates ONLAD Core works at x6.3 ∼ x25.4 lower power consumption while training computations are continuously executed.