A model is presented which relates the applied load and surface roughness to the integrity of metal-metal wafer-level thermocompression bonds. Using contact theory, the true contact area is calculated as a function of the applied load and surface roughness as characterized using atomic force microscopy. The relationship between the nominal and true contact areas quantifies the effects of applied load and surface roughness on the bond integrity of the bonded wafers as indicated by the dicing yield. Experiments on Cu–Cu bonds show that the true contact area provides a better indicator of bond integrity than either the nominal contact area or applied force, taken together or separately.

The increasing complexity and the scaling down of feature sizes for devices have led to the increasing dominance of interconnect delays in determining integrated circuit performance. One promising solution is to stack devices vertically, commonly known as 3D ICs. Copper is an attractive candidate for 3D applications as it can be both the bonding and interconnect material. This thesis explores the wafers bonding technique, thermocompression bonding, to create 3D ICs. This technique involves the application of pressure and temperature to forge a bond. In this work, copper thin films were used to bond two silicon substrates. Characterization of the bond process focused on the effects of bonding temperature (250 o C to 400 o C), applied load (400 to 10000 N) and surface roughness (total root-mean-square roughness of 1 nm to 14 nm). The resultant bond was quantified using a four-point bend test technique. High bond strength was obtained and the bond quality was found to improve with increases in the bond temperature and applied load, and with decreases in the surface roughness. However, nonideality in the load-displacement behavior was observed due to variation in the bond strengths and non-uniformity in the bonding. This is attributed to process issues such as dishing and non-uniform distribution of the true contact area. The true contact area between two contacting surfaces is found to be a small fraction of the nominal contact area. A contact model was developed to estimate this true contact area, taking into account the applied loads, the nominal contact areas, and the surface roughness of the pre-bond surfaces. The dicing yield of the bonded wafers was found to correlate with the true contact area and is directly proportional up to a maximum yield of 100%. In addition to the applied load, the surface roughness is also critical in obtaining good bonds between the bonded surfaces. A contact resistance test structure was fabricated to measure the contact resistance of the bonded interface. The contact resistances were shown to increase as surface roughness increases and/or as the applied load decreases. A contact resistance model was also developed to predict the contact resistance of a bonded interface, taking into account of the true contact area. It was shown that the model's prediction is close to the minimum value measured in each case but is about an order lower than the average value. This is likely to be because the model does not account for large-area non-uniformities in the fabrication and bonding processes, such as dishing effects. A contact resistance reduction phenomenon under high current density was also observed and is shown to be due to electro-migration rather than Joule heating effects. This work has demonstrated the viability of wafer-level thermo-compression bonding of Cu for fabricating 3D ICs. The contact model determines the process controls to achieve

Bonded Cu interconnects were stressed with increasing current while the contact resistance was measured. Interconnects with high initial contact resistance exhibited a contact resistance reduction phenomenon at a critical current density. The higher the initial contact resistance is, the lower the current required to trigger this phenomenon. Interconnects with low initial contact resistances exhibit this phenomenon only when stressed at a higher temperature. Electromigration is shown to be the most likely mechanism responsible for this phenomenon. This behavior can be used for low-temperature improvement of the quality of bonded interconnects for three-dimensional integrated circuits.