A variety of screening approaches have been proposed to diagnose epileptic seizures, using electroencephalography (EEG) and magnetic resonance imaging (MRI) modalities. Artificial intelligence encompasses a variety of areas, and one of its branches is deep learning (DL). Before the rise of DL, conventional machine learning algorithms involving feature extraction were performed. This limited their performance to the ability of those handcrafting the features. However, in DL, the extraction of features and classification are entirely automated. The advent of these techniques in many areas of medicine, such as in the diagnosis of epileptic seizures, has made significant advances. In this study, a comprehensive overview of works focused on automated epileptic seizure detection using DL techniques and neuroimaging modalities is presented. Various methods proposed to diagnose epileptic seizures automatically using EEG and MRI modalities are described. In addition, rehabilitation systems developed for epileptic seizures using DL have been analyzed, and a summary is provided. The rehabilitation tools include cloud computing techniques and hardware required for implementation of DL algorithms. The important challenges in accurate detection of automated epileptic seizures using DL with EEG and MRI modalities are discussed. The advantages and limitations in employing DL-based techniques for epileptic seizures diagnosis are presented. Finally, the most promising DL models proposed and possible future works on automated epileptic seizure detection are delineated.

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This paper reports on the application of the Walsh-Hadamard transform (WHT) for data compression in brain-machine/brain-computer interfaces. Using the proposed technique, the amount of the neural data transmitted off the implant is compressed by a factor of at least 63 at the expense of as low as 4.66% RMS error between the signal reconstructed on the external host and the original neural signal on the implant side. Based on the proposed idea, a 128-channel WHT processor was designed in a 0.18- μm CMOS process occupying 1.64 mm(2) of silicon area. The circuit consumes 81 μW (0.63 μW per channel) from a 1.8-V power supply at 250 kHz. A prototype of the proposed processor was implemented and successfully tested using prerecorded neural signals.

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