High substrate warpage can lead to unacceptable yield loss during chip attach in assembly, and cause high yield fallout during package mount on the circuit board. For the first time, through this work, the electrolytic copper (Cu) plating process in substrate manufacturing was shown to contribute significantly to package warpage. For a 14x14mm package, reducing the Cu plating rate (within the manufacturing operating window) resulted in 21% package warpage reduction, while a change in Cu plating solution provided an additional 6% reduction (total 27% reduction). Hence the Cu plating process and solution must be carefully scrutinized to minimize package warpage, specifically for thin packages (<1mm) where Cu stresses become a large contributing factor.