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This paper presents the design of an all-digital delay-locked loop (ADDLL) with duty-cycle correction using reusable time-to-digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide-operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18-μm complementary metal-oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8-V supply at 900 MHz. The peak-to-peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively.

SUMMARYIn conventional delay-locked loop circuits, the charge and discharge of the charge pump result in mismatched current reflecting the size of the static phase error. The static phase error between feedback clock and reference clock is likely to be within tens or hundreds of picoseconds (ps). We thus propose an approach using digital calibration methods to reduce the charge pump current mismatch by means of the setup time of the D-type flip flop. The setup time of D-type flip flop is determined and duplicated to detect the phase error between the reference clock and feedback clock. It results in a very small static phase error between the reference clock and feedback clock. This paper used a 0.18 μm CMOS process design, with a reference frequency of 700~900 MHz. The active area is 0.031 mm 2 , and the phase error after correction is less than 5 ps.

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