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This study presents a new virtual inductor current circuit to reduce circuit complexity, which is not necessary to sense inductance current directly. The buck converter was designed to produce an output voltage of 1.0–2.5 V for a 3.0–3.6 V input voltage. The load current range was from 100 mA to 500 mA. It was simulated and verified by SIMPLIS and MathCAD. The simulation results of this buck converter show that the voltage error is within 1%, and the recovery time is smaller than 2 ms for step-up and step-down load transients. Additionally, it achieves less than 26 mV overshoot at full-load step transient response. The circuit topology would be able to fabricate using TSMC 0.35 mm 2P4M CMOS technology. The control mechanism, implementation, and design procedure are presented in this paper.

This paper presents a novel buck converter with dual-loop control technology, which does not need to detect the inductor current directly. The structure of the control loops is easy to implement, one loop controls the output voltage, and the other controls the switching frequency. With the dual loops control mechanism, the output voltage and switching frequency can be accurately controlled only by measuring the output and input voltage, without sensing the inductor current. The buck converter can generate an output voltage of 1.0–2.5 V when the input voltage and load current are 3.0–3.6 V and 100–500 mA, respectively. The design was verified by SIMPLIS. The simulation results show that the switching frequency variation is less than 1% at the output voltage of 1.0–2.5 V. The recovery time is less than 1.5 μs during the load change. The circuit can be fabricated by using the TSMC 0.35μm 2P4M CMOS processes. The control scheme, theoretical analysis and circuit implementation are presented in this paper.

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This paper presents a buck converter with a novel constant frequency controlled technique, which employs the proposed frequency detector and adaptive on-time control (AOT) logic to lock the switching frequency. The control scheme, design concept, and circuit realization are presented. In contrast to a complex phase lock loop (PLL), the proposed scheme is easy to implement. With this novel technique, a buck converter is designed to produce an output voltage of 1.0–2.5 V at the input voltage of 3.0–3.6 V and the maximum load current of 500 mA. The proposed scheme was verified using SIMPLIS and MathCAD. The simulation results show that the switching frequency variation is less than 1% at an output voltage of 1.0–2.5 V. Furthermore, the recovery time is less than 2 μs for a step-up and step-down load transient. The circuit will be fabricated using UMC 0.18 μm 1P6M CMOS processes. The control scheme, design concept and circuit realization are presented in this paper.