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Abstract-A full study of three data formats including duobinary, PAM4, and NRZ is proposed to estimate the performance of the corresponding transceivers under different conditions. Transceiver prototypes designed and optimized for the three signalings are presented to evaluate their performance as well as the feasibility. The three transceivers have been tested thoroughly in Rogers and FR4 boards. Fabricated in 90-nm CMOS technology, all three transceivers achieve error-free operation with 20-Gb/s 2 31 1 PRBS data over 40-cm Rogers and 10-cm FR4 channels. General comparison reveals that the NRZ data still achieves the best performance at 20 Gb/s. Index Terms-Duobinary, pulse-amplitude modulation (PAM4), non-return-to-zero (NRZ), bit error rate (BER), backplane transceiver.

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The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than 72 dBc while consuming 88 mW from a 1.45-V supply.

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