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A fast stripe-based connected component labelling algorithm is proposed for binary image labelling. Stripe extraction strategy is used to transform the pixel-connected issues, which most of the previously proposed algorithms focused on, into stripe-connected issues. The stripe-union strategy treats the combination of the neighbouring stripes as the mergence of rooted trees. Finally, comparisons are performed with other famous fast labelling algorithms. The proposed algorithm has shown better performance than the state-of-the-art algorithm in real images test, while the auxiliary memory is not required at all compared with all competitors.

An efficient two-scan connected component labelling (CCL) algorithm is proposed for a general purpose graphics processing unit (GPGPU). Compared to other GPU CCL algorithm, this algorithm has three distinct features. First, block-based and run-based strategies are combined in the first scan to simplify the equivalence label resolving process. Secondly, a novel labelling method for the GPU is introduced by constructing a forest of rooted trees using only 16-bit value for each node. Thirdly, the whole algorithm can be implemented in the GPU shared memory and minimise global memory bandwidth consumption. Experiments show that the algorithm achieves a speedup of between two and five times compared to other state-of-the-art GPU and CPU CCL algorithms.

A novel line-based streaming labeling algorithm with its VLSI architecture is proposed in this paper. Line-based neighborhood examination scheme is used for efficient local connected components extraction. A novel reversed rooted tree hook-up strategy, which is very suitable for hardware implementation, is applied on the mergence stage of equivalent connected components. The reversed rooted tree hook-up strategy significant reduces the requirement of onchip memory, which makes the chip area smaller. Clock domains crossing FIFOs are also applied for connecting the label core and external memory interface, which makes the label engine working in a higher frequency and raises the throughput of the label engine. Several performance tests have been performed for our proposed hardware implementation. The processing bandwidth of our hardware architecture can reach the I/O transfer boundary according to the external interface clock in all the real image tests. Beside the advantage of reducing the processing time, our hardware implementation can support the image size as large as 4096*4096, which will be very appealing in remote sensing or any other high-resolution image applications. The implementation of proposed architecture is synthesized with SMIC 180nm standard cell library. The work frequency of the label engine reaches 200MHz.

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