For 28 nm node and below, implant layer patterning is becoming challenging with node shrinkage, due to decreasing critical dimension and usage of non-uniform reflective substrates without bottom anti-reflection coating (BARC). The ADI CD uniformity of a test feature is dramatically improved by adding BARC to reduce substrate reflection, nevertheless a prevalent LDD loop will not introduce BARC for the concern of cost and process complication reduction. The considerable bottom substrate reflectivity not only causes standing wave in photo resist but also introduces slight footing between the photo resist line and the substrate poly head if the substrate topography is rough (especially in the SRAM region). It is necessary to optimize the photo resist profile even under a very high bottom reflectivity. In this paper, several factors of the implant litho process that could impact the photo resist profile and line width roughness (LWR) are studied, and a comprehensive optimization based on these factors' splits test are defined and adopted in the 28 nm LDD loop litho process. Firstly we changed the mask CD to wafer CD bias and simultaneously modified the exposure dosage to meet the ADI target, which is based on our previous study that larger mask bias and over-dosage exposure will result in better photo resist profile. Secondly we studied the PR profile dependence on temperature of post exposure baking (PEB), we tried out the best temperature setting to improve photoresist footing. Thirdly we slightly shifted the focus offset during exposure away from the best focus defined by process FEM results, so that the photoresist profile is improved and meanwhile maintaining a large enough depth of focus for the process.

Implant level photolithography processes are becoming more and more challenging due to decreasing CD and photoresist edge placement requirements. In addition to the traditional proximity effects associated with the implant layer mask, the underlying active and gate layers can interact through a variety of mechanisms to influence the edge placement of the developed implant layer. For many implant layers, the impact of underlying topography cannot be subdued, because, because it is not desirable to employ bottom anti-reflection coating (BARC) for various reasons. Therefore, the implant OPC models calibrated on bare silicon wafers must include additional compensation components to counter the various substrate complexities from real device/design scenarios. In this paper, we show our systematic study on substrate effect (AA/STI) on implant level lithography CD printing including real wafer data analysis and simulation with wafer 3D OPC. Besides, we also show some study of the poly effect on CD. Based on the results, we generate an empirical model to match the substrate effect, and also proposed an approach with additional substrate-aware OPC rule to correct such effect.