No abstract

Keeping pace with the steady advances in the development of even finer gate length technologies, CMOS has established as preferred process for radio-frequency design that enables the integration of complex digital circuitry on the same die at reasonable costs in terms of required area and power consumption. A single-chip dual-band CDMA2000 receiver based on zero-IF architecture is presented. In addition to all required analog building blocks for reception in the North-American cellular and PCS bands (Band Class 0 and 1), the chip features a fully integrated synthesizer including VCOs for minimum external component count, analog anti-aliasing filters, a fully configurable digital-front-end (DFE), ∆Σ ADCs, a high-speed digital serial baseband (BB) interface, and a three-wire-bus configuration interface. The DFE's functionality includes samplerate-conversion, channel filtering, dynamic range control, and signal conditioning for data transmission via a digital interface between RFIC and baseband IC. The receiver IC with a die size of 8 mm 2 has been fabricated in 0.13-µm RF-CMOS and shows an error-vector-magnitude (EVM) of 3.1 % and a Rho of 0.998 at the digital baseband interface.978-2-87487-002-6

No abstract