System-On-Package (SOP) is a highly integrated systems packaging technology for convergent computing, communication, consumer, and bio-electronic functions in a single package or module. SOP aims to miniaturize systems by the integration of system-level components at microscale in the short term and nanoscale in the future. A key challenge for active and passive component integration is the demand for additional fine pitch wiring in the substrate for interconnecting these thin film embedded components. This adds to the already escalating need for high wiring density substrates driven by transistor density on the IC (Moore's Law). This paper addresses a critical process technology for SOP/microprocessor ultra-high density organic build-up substrates, namely, surface treatment of copper and dielectric in multilayer wiring. This process is critical for the challenges of processing and maintaining signal integrity at lines and spaces below 12ptm. A complete description of fine line and space fabrication and a novel copper adhesion process and its operating parameters are presented. We demonstrate this process with superior bonding strength through accelerated reliability testing. Results are shown not only state-of-the-art build-up films but also for highperformance substrates and prepregs in comparison to more traditional copper roughening treatment methods.

During the past two years, fine pitch copper wire bonding has finally entered high volume production. It is estimated that nearly 15% of all wire bonders used in production are now equipped for copper wire bonding. Most of these are used exclusively for copper wire bonding. In terms of pitch, copper wire is only barely lagging behind the most advanced gold applications. The most commonly used copper wire is 20um in diameter and 18um copper wire is already being used in mass production. Evaluations with even finer wire are underway. Although some technical challenges remain, many years of research have now resolved most of the problems associated with copper wire bonding and attention is beginning to shift from merely ensuring reliable manufacturing processes to optimizing processes for efficiency and throughput. The most advanced wire bonders now have pre-configured processes specifically designed for copper. In addition to throughput optimization, further cost reductions are being sought. Among these is the desire to eliminate the high-cost gold not just from the wire, but also from the substrate. On the substrate side the electronics packaging industry still works with electrolytic nickel / electrolytic (soft) gold (Ni/Au) for copper wire bond applications. This surface finish works with copper wire bonding but includes some disadvantages, such as:- Thick expensive Au layers of 0.1 to 0.4μm- Electrically connected pads (bussing for the plating) which requires added space on the substrate.- Pd-coated copper wire often delivers better results on gold covered finishes, but is two to three times more expensive as pure copper wire Furthermore electrolytic Ni/Au was not chosen for Cu wire bonding as a result of in-depth investigations for the most effective surface finish. The selection was made because it was the surface finish with the highest distribution in the market for wire bond packages. This paper is offering the results of a two company joint work regarding alternative copper wire bondable surface finishes. The result of the project is separated in 2 papers/publications. The first publication [1] presents the investigations with Cu wire bond pull forces and process windows of 23 different surface finish variations. The main aim was to identify alternative surface finishes for copper wire bonding. Within this study the surface finishes ENEP (Electroless Nickel/Electroless Palladium) and “Direct Electroless pure Pd on copper” (pure EP finish) was identified as copper wire bondable finishes with the pure Cu wire. The second part of the evaluation summarizes an in-depth study of copper wire bonding tests after thermal aging with ENEP and the pure EP surface finish using the pure copper wire. The results of this investigation does include results with pull forces after thermal aging and an IMC Investigation with FIB Pictures of the copper wire/surface finish connection in order to evaluate the reliability of such an interconnection.

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As a surface finish, electroless nickel / electroless palladium / immersion gold (ENEPIG) has received increased attention for both packaging/IC-substrate and PWB applications. With a lower gold thickness compared to conventional electroless nickel / immersion gold (ENIG) the ENEPIG finish offers the potential for higher reliability, better performance and reduced cost.[1,2] This paper shows the benefits of using a pure palladium layer in ENEPIG and ENEP (Electroless Nickel / Electroless Palladium) surface finishes in terms of physical properties and in terms of gold wire bonding and solder joint integrity.