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This paper presents a high performance design for ContextBased Adaptive Variable Length Coding (CAVLC) used in the H.264/ AVC standard. A two-stage encoder is proposed to make the scan and encode stage work simultaneously. The scan engine scans four coefficients at each cycle. Parallel encoder for four "levels" and parallel encoder for four "Run before" are adopted to accelerate the encode engine. Only 120 cycles at most are needed to process one MB. The proposed CAVLC encoder can support 4 Kx2 K@60 fps (frame per second) real-time encoding at 250 MHz and the gate count is about 32 k.

In this paper, a hardware/software co-design approach is proposed to parse the video bitstream which conforms to various video compression standards. The layered structure of the syntax elements in video bitstreams is analyzed. Then a hardware/software partition is proposed accordingly. Due to the high data rate, syntax elements in slice data and lower layers are commonly parsed by hardware. As for syntax elements in slice header and upper layers, we proposed a hw/sw co-design approach in order to combine the advantage of hardware acceleration and software flexibility. specific hardware accelerators are designed to parse these codes. But the parsing process of these codes in slice header and upper layer is controlled by software instead of hardware Finite state machine (FSM). This approach can speed up the process of Variable-Length Decoding (VLD) while it still has the flexibility to support multiple video coding standards.

This paper presents a high performance design for Context-Based Adaptive Va riable Length-Coding (CAVLC) used in the H.264/AVC standard. To reduce the cycles of processing one macroblock (MB), a two-stage residual encoder is proposed to make the scan and encode stage work simultaneously. The scan engine scans two coefficients at each cycle. Parallel encoder for two levels and parallel encoder for two runs are adopted to accelerate the encoder engine. Only 228 cycles at most are needed to process one MB. Due to the existence coded block pattern (CBP) decided skip block mode, our experiment shows only 160 cycles are needed on the average. The proposed CAVLC encoder can support 4Kx2K @30fps (frames per second) real-time encoding at 250 MHz and the gate count is only about 16k.

This paper presents a high performance VLSI design of Context-Based Adaptive Variable Length-Coding (CAVLC) for 4096x2160p@60fps H.264/AVC encoder. A parallel architecture is proposed to make the scan and encode stage work simultaneously. Four coefficients are scanned in parallel, and four Levels and Run_before are coded in parallel. From experimental results, only 120 cycles at most are needed to process one macroblock (MB), which reduce more than 50% cycles compare to state-of-the-art designs. The hardware implementation results show that the proposed design achieves real-time encoding at 250 MHz and the hardware cost is about 32k gates.