with the increasing of imaging sensor resolution, the captured images are becoming larger and larger, which requires higher image compression ratio. This paper analyzes some key points of this standard including nonlinear prediction, golomb coding and Run-Length coding, and discusses the performance in loss less compression of JPEG-LS. The comparison of this standard with other algorithms is also given.While discussing the hardware implementation based on FPGA, this paper presents the cache settings for reading and writing and timing control for the whole hardware design. The analysis shows that JPEG-LS loss less compression algorithm has a certain advantage in the imaging field.

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In high-speed real-time or non real-time signal processing systems, the use of mass memory for data cache is an indispensable part. It is also one of the focus and the difficulties in the realization of the system. Using the traditional method, the simulation will consume a lot of time, which would greatly reduce the efficiency of software design. To save time and resources, a simplified simulation model is put forward. Based on this module, a number of control signals are added to make the design more flexible. The paper is based on the overall idea of the design and taking a FLASH device as an example, the paper fully describes this idea. The design has proved that this is a more efficient method. The idea reflected can be widely used in the large-scale embedded system.