We propose a new signal security system and its VLSI architecture for real-time multimedia data transmission applications. We first define two bit-circulation functions for one-dimensional binary array transformation. Then, we exploit a chaotic system in generating a binary sequence to control the bit-circulation functions defined for performing the successive transformation on the input data. Each eight 8-bit data elements is regarded as a set and is fed into an 8×8 binary matrix being transformed on each row and each column of the matrix by these two bit-circulation functions such that the signal can be transformed into completely disordered data. The features of the proposed design include low computational complexity, regular operations suitable for low-cost VLSI implementation, high data security, and high feasibility for easy integration with commercial multimedia storage and transmission applications. We have performed Matlab simulation to verify the functional correctness of the proposed system. In implementing the system, a low-cost VLSI architecture has been designed, verified, and physically realized based on a 0.35 μm CMOS technology. The implementation results show that the proposed signal security system can achieve 117 Mbytes/s data throughput rate that is fast enough for real-time data protection in multimedia transmission applications

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In this paper, we have proposed a new cryptography system which combines both the position permutation and the value transformation encryption methods. Three good features involve in this system: (1) High security evaluated with the measure of fractal dimension, (2) The content of encrypted image is sensitive to the initial key, and (3) This system can easily defense against the exhaustive search attack. Besides, for the requirement of real-time in multimedia system, we also proposed the high performance reconfigurable architecture for this system as well as the IP core generator software. The proposed IP core generator can be parameterized by the parameters of system-type, packet size, throughput and security to create the proper IP core for the applications. All the architectures generated from the IP core generator have been verified; except for the coding guideline checking, there exist 100% code coverage. According to the UMC 0.18 um cell library, we further verified all the configurations of architecture for speed, area and power consumption as well as delivering the essential scripts. The verifications of all the configurations, the throughput can be ranged between 1.59 and 2.25 Gbps with the hardware cost of 0.54 and 3.92 mm2. Compared with the existing designs, the proposed design possesses performance enough for most of multimedia system applications.

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