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A CMOS down-conversion folded mixer for the radio frequency (RF) applications is presented. The proposed mixer composes of frequency doubling circuits, transconductance stages, and folded switching stages. With input 1.9GHz RF signals of -40dBm driven by 0.948GHz local oscillation (LO) signals of 0dBm, the mixer shows a good performance in both the high linearity and the low power consumption. The third-order input intercept point (IIP3) and the power consumption including the buffer stage are -3dBm and 6.4mW, respectively. The proposed mixer is designed and fabricated by tsmc 0.18μ μ μ μm 1P6M CMOS process with the size of 0.989 ͪ ͪ ͪ ͪ 0.559mm 2 .

This paper presents a fully integrated broadband low power high isolation subharmonic mixer. The proposed mixer achieves a double-balanced architecture by adopting a single-to-differential frequency-doubling technique, and improves port-to-port isolations. The mixer fabricated by tsmc 0.18 µm Mixed Signal CMOS process achieves maximum power conversion gain of 7.1 dB, input third-order intercept point (IIP3) of −6.9 dBm, input second-order intercept point (IIP2) of 33.5 dBm, and single side-band noise figure of −19.6 dB over the 2.3-5.8 GHz fourth generation of mobile phone communications standards (4G) frequency band. The LO-RF, LO-IF and RF-IF isolations are 82.8 dB, 66.5 dB and 62.3 dB, respectively. The measured power consumption is 2.95 mW at a 1.8 V power supply.