This paper presents a SPICE-based simulator, FlexiAnalyzer, for flexible thin-film transistor (TFT) circuits. This simulator performs four types of analysis: yield analysis, aging analysis, performance analysis, and weak spot analysis. This simulator considers three important effects: 1) threshold voltage variation of manufacturing process; 2) threshold voltage shift due to aging effect; and 3) mobility change due to bending effect. Six different OLED pixel drivers designed in 8-m amorphous silicon TFT technology were used in simulation results. The proposed tool provides a good solution for designers to evaluate the performance and yield of flexible TFT circuits.Index Terms-Flexible TFT circuits, spice, circuit analyzer, bending effect, aging effect.

In the routing architecture of a structured application-specific integrated circuit (ASIC), the crossbar is one of the most area-efficient switch blocks. Nevertheless, a dangling wire occurs when there is a routing bend in a crossbar switch. Dangling wires incur longer wire lengths as well as a higher interconnection capacitance. In this article, we tackle dangling wire issues for structured ASIC routability optimization. We first propose a compact graph model for crossbar-switch routing. With our graph model, switch connectivity relations can be removed to keep the 2D structured ASIC routing graph efficient and to speed up the runtime of our routing algorithm. Furthermore, we propose a heuristic dangling-wire-avoidance routing framework containing deferred pin assignment, Steiner point reassignment, and anchor pair insertion in order to minimize dangling wires and channel width. Finally, in order to take routing bends and channel width into account simultaneously, we propose concurrent and sequential integer linear programming (ILP) formulations and ILP variable/constraint degeneration techniques. The experimental results demonstrate that our proposed heuristic routing framework reduces dangling wires by 19%, channel width by 38%, and wire length by 13% to VPR using the crossbar switch (VPR-C). In addition, our sequential ILP router reduces dangling wires by 38%, channel width by 40%, and wire length by 15% compared to VPR-C. Thus, the runtime efficiency of our sequential ILP router is attractive for crossbar-switch structured ASIC routing.

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This paper presents a yield optimization tool, FlexiOptimizer, for flexible thin-film transistor (TFT) circuits. FlexiOptimizer considers three important effects: (1) process variation; (2) aging effect; and (3) bending effect. This SPICE-based optimizer applies response surface methodology (RSM) and orthogonal array (OA) techniques to size transistors so the yield is improved in aged and bent condition. This tool is demonstrated on two different designs: organic light emitting diode (OLED) pixel drivers and differential operational amplifiers (OPAMPs), in both amorphous silicon (a-Si) and Indium-Gallium-Zinc-Oxide (IGZO) TFT technologies. Index Terms-Analog circuit optimization, flexible TFT, orthogonal array, response surface methodology.