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We report on the development of a chemical mechanical planarization (CMP) process for thick damascene Ta structures with pattern feature sizes down to 100 nm. This CMP process is the core of the fabrication sequence for scalable superconducting integrated circuits at a 300 mm wafer scale. This work has established the elements of various CMP-related design rules that can be followed by a designer for the layout of circuits that include Ta-based coplanar waveguide resonators, capacitors, and interconnects for tantalum-based qubits and single flux quantum circuits. The fabrication of these structures utilizes a 193 nm optical lithography along with 300 mm process tools for dielectric deposition, reactive ion etch, wet-clean, CMP, and in-line metrology—all tools typical for a 300 mm wafer CMOS foundry. Theprocess development was guided by measurements of the physical and electrical characteristics of the planarized structures. Physical characterization such as atomic force microscopy across the 300 mm wafer surface showed that local topography was less than 5 nm. Electrical characterization confirmed low leakage at room temperature, and less than 12% within wafer sheet resistance variation for damascene Ta line widths ranging from 100 nm to 3  μm. Run-to-run reproducibility was also evaluated. Effects of process integration choices including the deposited thickness of Ta are discussed.

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