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The quality of surface finishing of CdZnTe wafers plays an essential role for the development of high-performance HgCdTe detectors. The surface processing of CdZnTe wafers is regarded as one of the most challenging tasks due to the soft-brittle material characteristics of CdZnTe crystals. The HgCdTe-based detector technology requires CdZnTe wafers with atomatically smooth surfaces because of the HgCdTe epitaxial growth. The wafer processing cycle consists of multiple steps starting with as-cut wafers from in-house grown CdZnTe boules followed by a series of consecutive polishing processes. CdZnTe wafers are then cleaned prior to wafer characterization and final inspection. The objective of this work is to demonstrate the current status of CdZnTe wafer processing technology at Aselsan through the as-cut wafers to the polished wafers promoted as finished products. The current wafer processing technology produces in-house grown epi-ready CdZnTe substrates with low surface roughness (<0.5 nm) and low flatness (<1 µm) in a repeatable fashion.