For high-quality flexible devices from printing processes based on Roll-to-Roll (R2R) systems, overlay alignment during the patterning of each functional layer poses a major challenge. The reason is because flexible substrates have a relatively low stiffness compared with rigid substrates, and they are easily deformed during web handling in the R2R system. To achieve a high overlay accuracy for a flexible substrate, it is important not only to develop web handling modules (such as web guiding, tension control, winding, and unwinding) and a precise printing tool but also to control the synchronization of each unit in the total system. A R2R web handling system and reverse offset printing process were developed in this work, and an overlay between the 1st and 2nd layers of ±5μm on a 500 mm-wide film was achieved at a σ level of 2.4 and 2.8 (x and y directions, respectively) in a continuous R2R printing process. This paper presents the components and mechanisms used in reverse offset printing based on a R2R system and the printing results including positioning accuracy and overlay alignment accuracy.

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In order to simplify a-Si TFT array manufacturing process, advanced 4 mask process of low resistant metal and new pixel electrode with improved unit process was developed. Slit photolithography with continuous dry etching process on the basis of metal dry etching cleared chronic problems of currently adopted 4 mask process and new combination of material and etchant for wet etching process made it possible to achieve stabilized wet etching and reduce total process steps. Our final version of a-Si TFT process architecture applicable to both notebook and monitor devices, will reinforce competitive power of TFT-LCD by improved displaying performance and ultimate process simplification.

High production cost of the TFT-LCDs is closely related to the complication of the fabrication process. To simplify the fabrication process, it is critical to reduce the number of mask-count. In this paper, 4-mask-count TFTarray process using slit (or gray-tone) photolithography technology is introduced. Various kinds of the geometrical slit designs and the exposure conditions have been simulated and experimentally optimized. By adopting this novel process, TFT channel is defined without using additional photolithography.

We propose a simulation model to explain two-dimensional field-effect operation of undoped poly-Si thin-film transistors (TFTs) under small drain voltages. Our model includes both thermionic-emission and drift-diffusion conduction processes. We calculated grain-boundary potential barriers, channel currents, and various device parameters depending on grain size and defect density. In order to validate our model, we compared calculated currents with experimental data for two types of poly-Si TFTs. We could obtain good current fits simultaneously in both subthreshold and linear regions by adopting proper densities of states in the poly-Si channels. We could also explain well the temperature-dependent current changes and the current activation energy versus the gate voltage. Finally, we succeeded in modeling the drain current under small drain voltages by using the combined transport process in the two-dimensional grain-boundary structure.