Highly crystalline 2D/3D‐mixed p‐transition metal dichalcogenide (TMD)/n‐Ga2O3 heterojunction devices are fabricated by mechanical exfoliation of each p‐ and n‐type material. N‐type β‐Ga2O3 and p‐type TMD separately play as a channel for junction field effect transistors (JFETs) with each type of carriers as well as materials for a heterojunction PN diode. The work thus mainly focuses on such ambipolar channel transistors with two different types of channel in a single device architecture. For more extended applications, the transparency of high energy band gap β‐Ga2O3 (Eg ≈ 4.8 eV) is taken advantage of, firstly to measure the electrical energy gap of p‐TMDs receiving visible or near infrared (NIR) photons through the β‐Ga2O3. Next, the p‐TMD/n‐Ga2O3 JFETs are put to high speed photo‐sensing which is achieved from the p‐TMD channel under reverse bias voltages on n‐Ga2O3. The photo‐switching cutoff frequency appears to be ≈16 and 29 kHz for visible red and NIR illuminations, respectively, on the basis of −3 dB photoelectric power loss. Such a high switching speed of the JFET is attributed to the fast transport of photo‐carriers in TMD channels. The 2D/3D‐mixed ambipolar channel JFETs and their photo‐sensing applications are regarded novel, promising, and practically easy to achieve.

We study a low voltage short pulse operating multilevel memory based on van der Waals heterostack (HS) n-MoSe2/n-MoS2 channel field-effect transistors (FETs). Our HS memory FET exploited the gate voltage (VGS)-induced trapping/de-trapping phenomena for Program/Erase functioning, which was maintained for long retention times owing to the existence of heterojunction energy barrier between MoS2 and MoSe2. More interestingly, trapped electron density was incrementally modulated by the magnitude or cycles of a pulsed VGS, enabling the HS device to achieve multilevel long-term memory. For a practical demonstration, five different levels of drain current were visualized with multiscale light emissions after our memory FET was integrated into an organic light-emitting diode pixel circuit. In addition, our device was applied to a synapse-imitating neuromorphic memory in an artificial neural network. We regard our unique HS channel FET to be an interesting and promising electron device undertaking multifunctional operations related to the upcoming fourth industrial revolution era.

Applications of 2D semiconductors have been extensively studied, much oriented to various electron devices. Recently, multivalue field-effect transistors (FETs) are also included among 2D-based electron device studies in consideration that multivalue FETs may resolve power consumption issues in future integrated circuits. Several n-channel devices are thus reported along with a few p-channel devices, while studies to achieve both n-and p-channel multivalue FETs are hardly found. Here, both n-and p-channel multivalue FETs are fabricated using p-MoTe 2 /n-MoS 2 heterostack channel architecture, where either p-or n-channel ternary value FET is reproducible by switching the stacking order of p-and n-channel layer. The main ternary value mechanism originates from resonant tunneling type injection and channel inversion, which take place during device operation. For a state-of-the-art device application in 2D electronics, a quaternary NAND logic circuit is for the first time demonstrated by integrating two ternary n-channel FETs, and a complementary ternary inverter is also fabricated by integrating multivalue p-channel and plain n-channel FET.

negative-capacitance (NC) effect [3] has recently attracted much attention. [4][5][6][7] NC-FETs incorporate ferroelectric (FE) on dielectric (DE) layers, [8][9][10][11][12][13][14][15][16][17][18] but they are obviously different from FE-gated or highk DE-gated transistors (as categorized in Table S1 in the Supporting Information). For NC-FETs, their operation relies on the anomalous polarization response of FE gate material to the external electric field. Although other types of novel FETs such as topological quantum FET, [19] tunnel FETs, [20,21] and impact ionization MOSFETs [22] have also been proposed as alternatives to overcome the same challenge, NC-FET has great advantages in its simplicity for device fabrication over the other FETs. Despite its great potential for reducing SS, NC-FETs usually exhibit hysteresis during operation, which is detrimental to logic device applications. The hysteresis originates from the bistable polarization configuration of the FE gate insulator. (FE-gated FET shows large hysteresis with low SS, while high-k DE-gate FET shows little hysteresis but a relatively large SS.) Recently, researchers have found that the proper capacitance matching between DE and FE layers can ensure the hysteresis-free device operation. [7,[23][24][25] However, the FE/DE capacitance matching is only feasible via a precise thickness control of FE and DE layers, which is often very difficult to achieve. Therefore, even with significant engineering efforts, the realization of hysteresis-free NC-FET with reduced SS has been challenging. Most of the Negative-capacitance field-effect transistors (NC-FETs) have gathered enormous interest as a way to reduce subthreshold swing (SS) and overcome the issue of power dissipation in modern integrated circuits. For stable NC behavior at low operating voltages, the development of ultrathin ferroelectrics (FE), which are compatible with the industrial process, is of great interest. Here, a new scalable ultrathin ferroelectric polymer layer is developed based on trichloromethyl (CCl 3 )-terminated poly(vinylidene difluoride-cotrifloroethylene) (P(VDF-TrFE)) to achieve the state-of-the-art performance of NC-FETs. The crystalline phase of 5-10 nm ultrathin P(VDF-TrFE) is prepared on AlO X by a newly developed brush method, which enables an FE/dielectric (DE) bilayer. FE/DE thickness ratios are then systematically tuned at ease to achieve ideal capacitance matching. NC-FETs with optimized FE/DE thickness at a thickness limit demonstrate hysteresis-free operation with an SS of 28 mV dec −1 at ≈1.5 V, which competes with the best reports. This P(VDF-TrFE)-brush layer can be broadly adapted to NC-FETs, opening an exciting avenue for low-power devices.