Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

As silicon-based electronics approach the limit of improvements to performance and capacity through dimensional scaling, attention in the semiconductor field has turned to graphene, a single layer of carbon atoms arranged in a honeycomb lattice. Its high mobility of charge carriers (electrons and holes) could lead to its use in the next generation of high-performance devices. Graphene is unlikely to replace silicon completely, however, because of the poor on/off current ratio resulting from its zero bandgap. But it could be used to improve silicon-based devices, in particular in high-speed electronics and optical modulators.

Chemical reactions at the solid electrolyte (SE) and Li metal interface form an interphase before electrochemical reactions occur. This study investigates the effects of the chemically formed interphase between Li metal and Li1.5Al0.5Ge1.5(PO4)3 (LAGP) on cell failures under various experimental conditions. LAGP forms a black interphase by chemically reacting with Li metal. The interphase comprises a stoichiometrically changed LAGP and Li-related oxides and behaves as a mixed ionic and electronic conductor with the electronic conductivity dominating. Thus, upon application of an electrical current to Li metal anode, most of the Li ions can be reduced at the SE side surface of the interphase rather than the Li metal side, causing a local volumetric increase that triggers cracks in the SE. This crack formation process continues the pulverization of SE, leading to a gradual increase in cell resistance. Under cell operating conditions, electrochemical reactions with the chemically formed interphase can lead to the mechanical deterioration of the SE, leading to cell failure. Furthermore, the chemically formed interphase between melted Li and LAGP above 200 °C induces a rigorous chemical reaction with Li that leads to a thermal runaway. The chemical stability of the SE against Li metal can strongly affect the solid-state cell’s electrical properties, mechanical integrity, and thermal stability.

We report on the interlayer screening effect of graphene using Kelvin probe force microscopy (KPFM). By using a gate device configuration that enables the supply of electronic carriers in graphene sheets, the vertical screening properties were studied from measuring the surface potential gradient. The results show layer-dependence of graphene sheets, as the number of graphene layers increases, the surface potential decreases exponentially. In addition, we calculate the work function-related information of the graphene layers using KPFM.

Device instabilities of graphene metal-oxide-semiconductor field effect transistors such as hysteresis and Dirac point shifts have been attributed to charge trapping in the underlying substrate, especially in SiO2. In this letter, trapping time constants around 87 μs and 1.76 ms were identified using a short pulse current-voltage method. The values of two trapping time constants with reversible trapping behavior indicate that the hysteretic behaviors of graphene field effect transistors are due to neither charge trapping in the bulk SiO2 or tunneling into other interfacial materials. Also, it is concluded that the dc measurement method significantly underestimated the performance of graphene devices.