Auger recombination [12,13] and energy transfer between QDs in films, which is required in QD-light emitting diode (LED) applications. [14][15][16][17] Second is the etching of an oxidized core prior to shell growth to prevent interfacial oxidation. [7,18,19] Finally, smoothing of core/shell interface by matching a shell with a similar lattice constant can be applied to avoid the generation of defect sites. [20,21] We synthesize InP/ZnSe/ZnS QDs having a thick ZnSe shell (with 8 monolayers). The QDs with thick ZnSe shell are effective for reducing energy transfer between neighboring QDs in respect of QD-LED applications. In this study, we present a simple but highly effective strategy to modulate the InP/ZnSe/ZnS QD shapes by controlling the shell reaction temperatures. The strategy of increasing the ZnSe shell-grown temperature accelerated the rates of shell growth. The synthesized two structures showed differences in morphology; one is a QD with an irregular shell (iQD), and the other is one with a regular isotropic shell (rQD). Especially, the rQDs have significantly improved the photoluminescence (PL) quantum yield (QY). Since the correlation between morphology modification and photophysical properties has been unexplored for InP-based core/shell QDs to the best of our knowledge, we scrutinized the ZnSe shell crystalline structures and PL properties of the InP/ZnSe/ZnS QDs with different shapes.Ensemble-averaged measurements have often been used to evaluate QD photophysical properties, [22][23][24][25] but they tend to overlook the nature of an individual QD or inter-dot interactions. To fully understand the charge carrier dynamics depending on the QD morphology, we investigated the photophysical properties of QDs on both ensemble and single dot levels. As a result, it was found that the shape-dependent QD PL efficiencies are governed by charge trapping dynamics. The ZnSe crystalline structure analyses verified that the fast ZnSe reaction on the InP core reduced facet-selective growth and eliminated stacking faults. Thus, we have concluded that the enhancement of PL QY in isotropic QDs has resulted from the removal of stacking faults. The pump energy-dependent transient absorption (TA) dynamics showed that the hot hole trapping was considerably suppressed in the iQDs. This spectroscopic evidence supports the supposition that the stacking faults in the InP/ZnSe crystalline structures act as structural defects to trap hot charge carriers. In this study, we provide a spectroscopic insight into the shape-dependent PL efficiency of InP-based QDs and the correlation between the hole trapping dynamics and the structural defects.Isotropic InP/ZnSe/ZnS quantum dots (QDs) are prepared at a high reaction temperature, which facilitates ZnSe shell growth on random facets of the InP core. Fast crystal growth enables stacking faults elimination, which induces anisotropic growth, and as a result, improves the photoluminescence (PL) quantum yield by nearly 20%. Herein, the effect of the QD morphology on photophysical properti...

We demonstrate that the surface roughness of metallorganic chemical vapor deposited RuO 2 is significantly decreased by plasma treatment before the deposition of the film. The root mean square (rms) value of the surface roughness is decreased from ~25 to 3 nm by applying O 2 plasma for 5 min prior to the deposition of an ~200 nm thick layer of RuO 2 . Other plasma gases such as H 2 and Ar also decrease the rms value of the surface roughness, but are not as effective as O 2 plasma. The decrease of surface roughness is attributed to the enhancement of nucleation density at the initial stages of film growth. © 1998 The Electrochemical Society. S1099-0062(98)06-055-6. All rights reserved.Manuscript submitted June 15, 1998; revised manuscript received September 10, 1998. Available electronically October 12, 1998. RuO 2 has been chosen as one of the strong candidate materials for an electrode of the high dielectric constant oxides such as barium strontium titanates and lead zirconium titanates, due to such advantages as low electrical resistivity (46 µΩ cm), high interfacial stability with dielectric oxide material, excellent diffusion barrier property against oxygen, and good dry etchability. This motivates many researchers to develop the RuO 2 thin film deposition process. 1-3 While thin films of RuO 2 have been commonly deposited by reactive sputtering process, the development of chemical vapor deposition (CVD) process using metallorganic source gases is now underway. 1,[4][5][6] The CVD process, as compared to the sputtering process, is preferable for obtaining a conformal coverage, which is a critical requirement for the materials to be used in an advanced integrated circuit process. Also, films deposited by CVD show inherently low stress levels as compared to sputter deposited films. However, the RuO 2 films deposited by CVD show extensive surface roughness 1,4 which is detrimental in many applications. This is especially true when the material is used as a lower electrode material. In general, this extensive surface roughness is attributed to large grain size development during deposition, which originates from the low nucleation rate as compared to the grain growth rate. For instance, the average grain size of the RuO 2 deposited by CVD is about 500 nm, which is an order of magnitude larger than that of sputter deposited RuO 2 . 1,4 Apparently, to reduce the surface roughness, one must develop a method to increase the nucleation rate at the initial stages of film growth during the CVD process.In this paper, we propose just such a method to enhance the nucleation rate at the initial stages of film growth. This method is based on utilizing a plasma treatment of the substrate prior to CVD of RuO 2 film, either with or without applying bias voltages. Also, the effects of using different gases, oxygen, hydrogen, and argon, to generate plasma are compared.Experimental Figure 1 shows a schematic diagram of the CVD system that was used for the deposition of the film. The chamber is divided into two parts; the upper pa...

Tunable multilevel gate oxide capacitance and flat‐band voltage shift characteristics in double‐floating‐gate metal–oxide–semiconductor (DFG‐MOS) capacitors are investigated for non‐volatile memory and programmable logic device applications. The DFG‐MOS capacitor with the structure of Ag(control gate)/CeO2(upper control oxide)/Al(upper FG)/CeO2(lower control oxide)/Pt(lower FG)/HfO2(tunneling oxide) on n‐Si substrate, that is Ag/CeO2/Al/CeO2/Pt/HfO2/n‐Si, exhibits three capacitance states as a result of reversible formation and rupture of conducting filaments at serially stacked Ag/CeO2/Al and Al/CeO2/Pt capacitors upon applying positive and negative gate voltages, respectively. In contrast, the DFG‐MOS capacitor with Ag/CeO2/Pt/HfO2/Pt/HfO2/n‐Si employing inert Pt upper and lower FGs exhibits two capacitance states via the formation and rupture of filament only at the upper Ag/CeO2/Pt stack. Instead, it accompanies a flat‐band voltage shift by electrical charging at the lower FG of Pt. The proposed devices operate with tunable multilevel gate oxide capacitance and flat‐band voltage shift associated with filament formation inside gate stacks and electrical charging with respect to the constituent materials of the FGs. These results pave the way for potential application to non‐volatile memory and programmable MOSFET logic device with tunable gate oxide capacitance, without relying solely on the electrical charging used in the current flash‐type memory.

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Conformal Amorphous Carbon Ultrathin Cu diffusion barriers with high conformality have gained great attention for next‐generation ultrahigh‐density semiconductor device miniaturization. In article number 2110454, Sun Hwa Lee, Rodney S. Ruoff, Ki‐Bum Kim, Sang Ouk Kim, and co‐workers introduce a handy and reliable method for the preparation of conformal amorphous carbon (a‐C) barrier layers with nanometer‐level thickness. A polystyrene brush layer is grafted onto a 3D copper structure with self‐limiting chemistry, and subsequent carbonization yields large‐area uniform 1 nm‐level a‐C layers with excellent Cu blocking performance.