This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC (Context-based Adaptive Binary Arithmetic Coding) encoding. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 5.68K and maximum clock frequency is 1.11GHz. It processes the 2 bins per clock cycle. Maximum processing speed increased by 22% from existing hardware architectures. And Gate count has been reduced by 31%.

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC (Context-based Adaptive Binary Arithmetic Coding) encoding. UHD (Ultra High Definition) images require very high throughput for standard video encoder. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing, making parallel processing difficult, because of the high dependency between data. The function of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. In addition, it generates an information bit for outputting a bitstream, and outputs a variable bitstream in one cycle. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog-HDL and synthesized in 65nm technology. Its gate count is 11.2K and maximum clock frequency is 625MHz. It processes 4 Bins per clock cycle, with a 36% increase in maximum processing speed compared to existing hardware architectures.