Abstruct-The Cascade Correlation [l] is a very flexible, efficient and fast algorithm for supervised learning. It incrementally builds the network by adding hidden units one at a time, until the desired input/output mapping is achieved. It connects all the previously installed units to the new unit being added. Consequently, each new unit in effect adds a new layer and the fan-in of the hidden and output units keeps on increasing as more units get added. The resulting structure could be hard to implement in VLSI, because the connections are irregular and the fan-in is unbounded. Moreover, the depth or the propagation delay through the resulting network is directly proportional to the number of units and can be excessive.We have modified the algorithm to generate networks with restricted fan-in and small depth (propagation delay) by controlling the connectivity. Our results reveal that there is a tradeoff between connectivity and other performance attributes like depth, total number of independent parameters, learning time, etc. When the number of inputs or outputs is small relative to the size of the training set, a higher connectivity usually leads to faster learning, and fewer independent parameters, but it also results in unbounded fan-in and depth. Strictly layered architectures with restricted connectivity, on the other hand, need more epochs to learn and use more parameters, but generate more regular structures, with smaller, limited fan-in and significantly smaller depth (propagation delay), and may be better suited for VLSI implementations. When the number of inputs or outputs is not very small compared to the size of the training set, however, a strictly layered topology is seen to yield an overall better performance.

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Standard automated test equipment (ATE) for radio frequency (RF) transceiver production testing of today is limited by digital signal processing and data transfer. These constraints can be considerably relaxed by the application of new technology based on field programmable gate array (FPGA). The methods proposed are capable of handling all tasks flexibly and at-speed. FPGA hardware resources are embedded into available ATE environment and support modular signal processing as well as highspeed interfacing. Avoiding any ATE upgrades, the costs for RF transceiver production testing can be driven to an absolute minimum that is achievable.