Relational Coarsest Partition Problems (RCPPs) play a vital role in verifying concurrent systems. It is known that RCPPs are P-complete and hence it may not be possible to design polylog time parallel algorithms for these problems.In this paper, we present a parallel algorithm for RCPP, in which its associated label transition system is assumed to have m transitions and n states. This algorithm runs in O(n 1+ ) time using m n EREW PRAM processors, for any fixed < 1. This algorithm is analogous and optimal with respect to the sequential algorithm of Kanellakis and Smolka. The same algorithm runs in time O(n log n) using m log n log log n CRCW PRAM processors. We also describe implementation and experimental results on performance of our algorithm.

Code generation from hybrid system models is a promising approach to producing reliable embedded systems. This approach presents new challenges as the precise semantics of the model are hard to capture in the code. A framework for generating code was introduced for single threaded/processor environments. Here, we extend it by considering code generation for distributed environments. We also define criteria for faithful implementation of the model. To this end, we define faulty and missed transitions. For preventing faulty transitions, we build on the idea of instrumentation we have developed for sound simulation of hybrid systems. Finally, we present sufficient conditions to avoid missed transitions and provide examples. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

The performance of a parallel algorithm depends in part on the interconnection topology of the target parallel system. An interconnection network is called reconfigurable if its topology can be changed between different algorithm executions. Since communication patterns vary from one parallel algorithm to another, a reconfigurable network can effectively support algorithms with different communication requirements. In this paper, we describe how to generate a network topology that is optimized with respect to the communication patterns of a given task. The algorithm presented takes as input a task graph and generates as output a topology that closely matches the given input graph. The topologies generated by our algorithm are analyzed with respect to optimum interconnection topologies for the best, worst, and average cases. Simulation results verify the average case performance prediction and confirm that, on the average, the optimum topologies are generated.Index Terms-Degree constrained connected graph, degree constrained subgraph, mapping algorithm, reconfigurable interconnection network, synthesis algorithm.OO18-9340/88/06OO-0691$01 .OO 0 1988 IEEE Insup Lee (S'82-M'82-S'82-M'83) received the B.

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