We rethink DRAM power modes by modeling and characterizing inter-arrival times for memory requests to determine the properties an ideal power mode should have. This analysis indicates that even the most responsive of today's power modes are rarely used. Up to 88% of memory is spent idling in an active mode. This analysis indicates that power modes must have much shorter exit latencies than they have today. Wake-up latencies less than 100ns are ideal. To address these challenges, we present MemBlaze, an architecture with DRAMs and links that are capable of fast powerup, which provides more opportunities to powerdown memories. By eliminating DRAM chip timing circuitry, a key contributor to powerup latency, and by shifting timing responsibility to the controller, MemBlaze permits data transfers immediately after wake-up and reduces energy per transfer by 50% with no performance impact. Alternatively, in scenarios where DRAM timing circuitry must remain, we explore mechanisms to accommodate DRAMs that powerup with less than perfect interface timing. We present MemCorrect which detects timing errors while MemDrowsy lowers transfer rates and widens sampling margins to accommodate timing uncertainty in situations where the interface circuitry must recalibrate after exit from powerdown state. Combined, MemCorrect and MemDrowsy still reduce energy per transfer by 50% but incur modest (e.g., 10%) performance penalties.

Today's high performance computing memory systems mainly consist of with DDR3 DRAMs offering 800Mb/s to 1600Mb/s data rates. Extending the performance of these main memory systems beyond the current data rate is quite challengeable as the signal integrity issues with physical channel remains relatively constant compared to the device performance which improves as process advances. This paper presents three key technologies which help the current memory architecture to reach the data rates of 1600~3200Mb/s without sacrificing memory capacity, increasing power consumption, or switching to more advanced differential signaling. These key features include FlexPhase™ timing adjustment to eliminate trace length matching, dynamic point-to-point signaling to increase memory capacity at high data rates, and near ground signaling to reduce IO signaling power. This paper demonstrates the benefits of these features from signal and power integrity point of view. I. CHALLENGES OF MAIN MEMORY SYSTEM DESIGNSDriven by recent multi-core computing, virtualization and processor integration trends, the data rate of a next generation main memory system for in high-end computer and workstation applications is expected to reach 3200Mb/s. In order to minimize system cost and provide backward compatibility, single-ended signaling based on Stub-Series Terminated Logic (SSTL) is the logic choice for next generation main memory I/O interfaces. Unfortunately, as the target data rate for memory interface continues to increase, signal integrity issues such as crosstalk, simultaneous switching output (SSO) noise, and reference voltage (VREF) noise, have become major limiting factors for potential data rates in high-speed memory interfaces [1].In addition to these conventional signal integrity issues, the main memory applications pose additional challenges due to the signal noise generated by multiple memory module loadings. In these multi-drop topologies, the major factor that determines the maximum speed of the memory bus is the worst-case loading characteristics in which all connectors are fully populated with memory modules. As a consequence, the number of modules that can be supported in a multi-drop architecture decreases with increasing bus speed. Fig. 1 shows the number of device drops per data pin versus data rate. As illustrated in this figure, the high data rate prohibits any multi-drops beyond 1333 or 1600Mb/s. This limitation has the effect of reducing the total system memory capacity. As such, alternative methods for achieving high capacity are desirable. This paper introduces three key technologies to enhance the current DDR3 technology to beyond 1600Mb/s [3]. The FlexPhase™ technology removes significant timing errors extending the potential data rate. The dynamic point-to-point technology enables multiple memory modules to be implemented as point-to-point signaling to increase the memory capacity. Finally, the near ground signaling technology reduces the total I/O interface power without sacrificing the signal quality. To demonstr...