Terrestrial LiDAR emerges as a main mapping technology for indoor 3D cadastre, cultural heritage conservation and, building management in that it provides fast, accurate, and reliable 3D data. In this paper, a new 3D modeling method consisting of segmentation stage and outline extraction stage is proposed to develop indoor 3D model from the terrestrial LiDAR. In the segmentation process, RANSAC and a refinement grid is used to identify points that belong to identical planar planes. In the outline tracing process, a tracing grid and a data conversion method are used to extract outlines of indoor 3D models. However, despite of an improvement of productivity, the proposed approach requires an optimization process to adjust parameters such as a threshold of the RANSAC and sizes of the refinement and outline extraction grids. Furthermore, it is required to model curvilinear and rounded shape of the indoor structures.

Historically when we used to manufacture semiconductor devices for 45 nm or above design rules, IC manufacturing yield was mainly determined by global random variations and therefore the chip manufacturers / manufacturing team were mainly responsible for yield improvement. With the introduction of sub-45 nm semiconductor technologies, yield started to be dominated by systematic variations, primarily centered on resolution problems, copper/low-k interconnects and CMP. These local systematic variations, which have become decisively greater than global random variations, are design-dependent [1, 2] and therefore designers now share the responsibility of increasing yield with manufacturers / manufacturing teams. A widening manufacturing gap has led to a dramatic increase in design rules that are either too restrictive or do not guarantee a litho/etch hotspot-free design. The semiconductor industry is currently limited to 193 nm scanners and no relief is expected from the equipment side to prevent / eliminate these systematic hotspots. Hence we have seen a lot of design houses coming up with innovative design products to check hotspots based on model based lithography checks to validate design manufacturability, which will also account for complex two-dimensional effects that stem from aggressive scaling of 193 nm lithography. Most of these hotspots (a.k.a., weak points) are especially seen on Back End of the Line (BEOL) process levels like Mx ADI, Mx Etch and Mx CMP. Inspecting some of these BEOL levels can be extremely challenging as there are lots of wafer noises or nuisances that can hinder an inspector's ability to detect and monitor the defects or weak points of interest. In this work we have attempted to accurately inspect the weak points using a novel broadband plasma optical inspection approach that enhances defect signal from patterns of interest (POI) and precisely suppresses surrounding wafer noises. This new approach is a paradigm shift in wafer inspection by leveraging systematic defect locations for high sensitivity inspection, thereby enhancing the discovery and monitoring of yield-limiting defects at traditional optical inspection throughput.

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