This study focused on predicting the fatigue life of an insulated gate bipolar transistor (IGBT) power module for electric locomotives. The effects of different wiring technologies, including aluminum wires, copper wires, aluminum ribbons, and copper ribbons, on solder fatigue life were investigated to meet the high power requirement of the IGBT module. The module's temperature distribution and solder fatigue behavior were investigated through coupled electro-thermo-mechanical analysis based on the finite element method. The ribbons attained a chip junction temperature that was 30° C lower than that attained with conventional round wires. The ribbons also exhibited a lower plastic strain in comparison with the wires. However, the difference in plastic strain and junction temperature among the different ribbon materials was relatively small. The ribbons also exhibited different crack propagation behaviors relative to the wires. For the wires, the cracks initiated at the outmost edge of the solder, whereas for the ribbons, the cracks grew in the solder layer beneath the ribbons. Comparison of fatigue failure areas indicated that ribbon bonding technology could substantially enhance the fatigue life of IGBT modules and be a potential candidate for high power modules.

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In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.

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