No abstract

In this paper the use of the EPE metric directly in the process optimization method for a DRAM use case has been researched. We show that EPE-aware optimization, using scanner dose and overlay control sub-recipes, is outperforming conventional optimization in terms of EPE Dies in Spec. Hence, it can be expected that also device yield can be improved by EPE-aware control.

During metrology overlay recipe setup typically a wide range of different target designs are present to select from. The main goal of recipe setup is to select the most accurate target type-recipe combination at ADI (after develop inspection) without additional external information that can be used for production on a large set of wafers. We will introduce a method based on blind source separation to disentangle the contributions of target asymmetry and the overlay of the targets. Based on this separation, the most accurate target-recipe combination can be selected. On top of selecting the most accurate target-recipe combination, it is important to stabilize the difference between the overlay on device and the overlay as measured on the target. In order to increase that stability we will introduce advanced algorithms in the ADI measurements that use measured asymmetry parameters to correct for inline target asymmetry variation. We will show a metrology to device matching improvement of up to 40% on product wafers.