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The paper presents design and implementation of a silicon particle detector array with the derived closed form equations of signal-to-noise ratio (SNR) and crosstalk voltages. The noise analysis demonstrates the effect of interpixel capacitances (IPC) between center pixel (where particle hits) and its neighbouring pixels, resulting as a capacitive crosstalk. The pixel array has been designed and simulated in a 180 nm BCD technology of STMicroelectronics. The technology uses the supply voltage (VDD) of 1.8 V and the substrate potential of −50 V. The area of unit pixel is 250×50 μm2 with the substrate resistivity of 125 Ωcm and the depletion depth of 30 μm. The mathematical model includes the effects of various types of noise viz. the shot noise, flicker noise, thermal noise and the capacitive crosstalk. This work compares the results of noise and crosstalk analysis from the proposed mathematical model with the circuit simulation results for a given simulation environment. The results show excellent agreement with the circuit simulations and the mathematical model. The average relative error (AVR) generated for the noise spectral densities with respect to the simulations and the model is 12% whereas the comparison gives the errors of 3% and 11.5% for the crosstalk voltages and the SNR results respectively.