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In this paper, effects preceding a latch-up fault in insulated gate bipolar transistors (IGBTs) are studied. Primary failure modes associated with IGBT latch-up faults are reviewed. Precursors to latch-up, primarily an increase in turn-off time as a consequence of elevated junction temperature, are examined for an IGBT. The relationship between junction temperature and turn-off time is explained by modeling the parasitic properties of an IGBT. A metric is derived from the model to standardize the relative estimates in junction temperature from measurements of turn-off time. To evaluate the effects preceding latch-up in-situ, seeded fault testing is conducted on a three-phase power inverter using aged transistors induced with a fault located in the die-attach solder layer. Experimental results demonstrated the feasibility of using the proposed metric as a precursor to transistor latch-up.

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